基于NIOS Ⅱ多核技术的BP神经网络的硬件实现方法研究
摘要
人工神经网络技术是智能信息处理领域研究的热点问题之一。目前,人工神经网络的实现方法主要是基于通用计算机的软件仿真,其缺点在于无法应用于某些对体积、稳定性、功耗等要求严格的嵌入式领域。针对这一问题,本文采用NIOS多核技术来研究神经网络的硬件实现方法是非常有必要的。
本文首先介绍了人工神经网络、BP神经网络算法、SOPC技术、NIOS多核处理器之间通信技术的相关概念及其发展状况;其次阐述了整个系统的硬件结构及芯片相关模块的功能;再次介绍了采用基于NIOS多核技术实现的BP网络进行正弦曲线拟合的设计过程,绘制了软件的设计流程;最后给出了正弦曲线的拟合结果。
在深化人工神经网络理论研究前提下,深入探讨人工神经网络硬件实现方法,从而扩展了人工神经网络的应用领域,为生物神经网络的进一步研究提供有效的仿真平台,对促进人工神经网络乃至智能信息处理技术的发展具有十分重要的理论意义和工程实践价值。
Artificial Neural Networks(ANN) is one of the hot problems in intelligence. information process area.At present,the implementation of ANN is based on the soft simulation with general purpose computer,so it can not be used in some embedded system which has limits of size,stability,power and other demanding.To solve this problem,this research uses NIOS microprocessor technology to study the hardware implementation of BP neural network.
First,ANN is introduced in the paper,as well as the BP neural network,the SOPC technology and the communication technology among NIOS microprocessors. Second,the hardware architecture is expounded,as well as the functional module of chip.Third,the design process of using the BP neural network,which is implemented with NIOS multiprocessor technology,to fit a sine curve is introduced.The flow of software design is also given.Finally,the result is presented and discussed.
With the intensive study of ANN,the hardware implementation of ANN methods is researched deeply.ANN applications are expanded.An effective simulation platform for the biological neural network will be provided for further research.The research which will promote the development of ANN and the intelligent information processing technology,offers important theoretical significance and engineering value.
本文首先介绍了人工神经网络、BP神经网络算法、SOPC技术、NIOS多核处理器之间通信技术的相关概念及其发展状况;其次阐述了整个系统的硬件结构及芯片相关模块的功能;再次介绍了采用基于NIOS多核技术实现的BP网络进行正弦曲线拟合的设计过程,绘制了软件的设计流程;最后给出了正弦曲线的拟合结果。
在深化人工神经网络理论研究前提下,深入探讨人工神经网络硬件实现方法,从而扩展了人工神经网络的应用领域,为生物神经网络的进一步研究提供有效的仿真平台,对促进人工神经网络乃至智能信息处理技术的发展具有十分重要的理论意义和工程实践价值。
Artificial Neural Networks(ANN) is one of the hot problems in intelligence. information process area.At present,the implementation of ANN is based on the soft simulation with general purpose computer,so it can not be used in some embedded system which has limits of size,stability,power and other demanding.To solve this problem,this research uses NIOS microprocessor technology to study the hardware implementation of BP neural network.
First,ANN is introduced in the paper,as well as the BP neural network,the SOPC technology and the communication technology among NIOS microprocessors. Second,the hardware architecture is expounded,as well as the functional module of chip.Third,the design process of using the BP neural network,which is implemented with NIOS multiprocessor technology,to fit a sine curve is introduced.The flow of software design is also given.Finally,the result is presented and discussed.
With the intensive study of ANN,the hardware implementation of ANN methods is researched deeply.ANN applications are expanded.An effective simulation platform for the biological neural network will be provided for further research.The research which will promote the development of ANN and the intelligent information processing technology,offers important theoretical significance and engineering value.
引文
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[2]Hopfield,J.J.,D.Tank.Computing with neural circuits[C].A model Science.1986,233:624- 633.
[3]Nordstrom,T.B.Svensson.Using and designing massively parallel computers for artificial neural networks[C].Journal of Parallel and Distributed Computing.1992,14(3):260-285.
[4]Y.Hirai.Hardware implementations of neural networks[J].Neurocomputing.1993(5):3- 16.
[5]N.Sundarajan,P.Satchandran.Parallel Architectures for Artificial Neural Networks[J].IEE Press.California.1998.
[6]Sund Su Kim,Seul Jung.Hardware Implementation of Real Time Neural Network Controller with a DSP and an FPGA[C].IEEE International Conference on Robotics and Automation.2004,5(4):3161-3165.
[7]杨期鹤,曹年红,陆佶人.基于DSP的BP神经网络的硬件实现[J].信号处理.1998,14(2).
[8]刘丁,万伯任.神经网络硬件研究的现状与趋势[J].计算机应用.1994(1).
[9]王剑,万冬梅,毛宗源.新型联想记忆神经网络的硬件实现研究[J].计算机工程与应用.2003.14.
[10]Cosmin.Hardware neural network-Building Neural Networks with MC431 DSP board[C].8th International Conference on Development and application systems.2006(5).
[11]Adang,Suwandi Ahmad etc.Design and implementation of Parallel Batch-mode Neural Network on Parallel Virtual Machine[C].Proceedings of Industrial Electronics Seminar.1999(10).
[12]Hendrik C A M,Withagen.Neural Networks:Analog VLSI Implementation and Learning Algorithms[D].Ph.D Thesis,Eindhoven,1997.
[13]高丽娜,邱关源.一种连续可调权值CMOS神经网络[J].电子学报.1998,26(2):120-122.
[14]Bernabe Linares-Barranco,et al.A Modular T-Mode Design Approach for Analog Neural Network Hardware Implementations and learning algorithm[J].IEEE Journal of Solid State Circuit.1992,27(5):701-712.
[15]B.M.Wilamowski,J.Binfet,M.O.Kaynak.VLSI Implementation of Neural Networks[]].Int.J.Neural Syst.2000,10(3):191-197.
[16]梁艳,靳东明.基于CMOS模拟电路的径向基函数神经网络[J].半导体学报.2008,29(2).
[17]刘常澎,刘峰,谢学智,庞维珍.可编程细胞神经网络硬件实现及应用研究[J].电子学报.2000,28(4).
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[19]Murray,A.F.,et al.Pulse Stream VLSI Neural Networks[J].IEEE Micro.1994,6:29-38.
[20]Fernando Morgado Dias et al.Artificial neural networks:a review of commercial hardware[J].Engineering Applications of Artificial Intelligence(Elsevier Science).2004,17:945-952.
[21]万以华.半导体神经计算机硬件实现研究及在全方位实物识别中的应用[D]:[硕士学位论文].杭州:浙江工业大学,2006,4.
[22]B.E.Boser,E.Sackinger,J.Bromley.An analog neural network processor with programmable topology[C].IEEE J.Solid State Circ.1991,26(12):2017-2025.
[23]B.E.Boser,E.Sackinger,J.Bromley.Hardware Requirements for Neural Network Pattern Classifier[C].IEEE Micro.1992(2):32-40.
[24]王守觉,曹文明.半导体神经计算机的硬件实现及其在连续语音识别中的应用[J].电子学报.2006,34(2):267-271.
[25]Valentina Salapura,Michael Gschwind,et al.A fast FPGA implementation of a general purpose neuron[C].Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications.1994:175-182.
[26]Wolf,D.F.,Romero,R.A.F.,Marques,E.Using Embedded Processors in Hardware Models of Artificial Neural Networks[C].Proceedings of SBAI 2001:78-83.
[27]Ferreira P,Ribeiro P,Antunes A,et al.Artificial neural networks processor:a hardware implementation using a FPGA[C].Proceedings of the 4th International Conference on Field Programmable Logic and Applications.Antwerp.2004:1084-1087.
[28]Wang Q,Yi B,Xie Y,et al.The hardware structure design of perceptron with FPGA implementation[C].Proceedings of IEEE International Conference on Systems,Man and Cybernetics.2003:762-767.
[29]李昂,王沁等.基于FPGA的神经网络硬件实现方法[J].北京科技大学学报.2007,29(1).
[30]魏刚,韩建国.基于FPGA的可重构软测量系统硬件设计[J].仪器仪表用 户.2006,13(4).
[31]James-Roxby,P.,B.A.Blodget.Adapting constant multipliers in a neural network implementation[C].Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines,2000:335-336.
[32]Zhu,J.M.,G.J.Gunther,B.K..Towards an FPGA based reconfigurable computing environment for neural network implementations[C].Proceedings of Ninth International Conference on Artificial Neural Networks.1999,2:661-666.
[33]Xiaoguang LI,Medhat Moussa,Shawki Areibi.Arithmetic formats for implementing Artificial Neural Networks on FPGA[J].Canadian Journal of Electrical and Computer Engineering.2006(1):31-40.
[34]Marchesi,M.,et al.Fast neural networks without multipliers[J].IEEE Transactions on Neural Networks,1993.4(1):53-62.
[35]Reyneri,L.M.Theoretical and implementation aspects of pulse streams:an overview[C].Proceedings of the Seventh International Conference on Microelectronics for Neural,Fuzzy and Bio-Inspired Systems.1999:78-89.
[36]Hikawa,H.A new digital pulse-mode neuron with adjustable activation function[J].IEEE Transactions on Neural Networks.2003.14:236-242.
[37]潘松,黄继业等.SOPC技术实用教程[M].北京:清华大学出版社,2005.
[38]Altera Corp.NIOS Ⅱ Processor Reference Handbook[G].Altera,2005.
[39]Altera Corp.NIOS Ⅱ Software Developer' s Handbook[G].Altera,2005.
[40]Altera Corp.Avlon Interface Specification[G].Altera,2005.
[41]Altera Corp.CycloneⅡ Device Handbook[G].Altera,2005.
[42]Altera Corp.Creating Multiprocessor NIOS Ⅱ System Tutorial[G].Altera,2005.
[43]Altera Corp.Configuration Handbook[G].Altera,2005.
[44]Altera Corp.NIOSⅡ Custom Instruction User Guide[G].Altera,2005.
[45]PicoBlaze 8-bit Embedded Microcontroller User Guide[G].Xilinx,2005.
[46]朱剑英.智能系统非经典数学方法[M].武汉:华中科技大学出版社,2001.
[47]李兰英等.NIOS Ⅱ嵌入式软核SOPC设计原理及应用[M].北京:北京航空航天大学出版社.2006.
[48]郭书军等.嵌入式处理器原理及应用-NIOS系统设计和C程序设计[M].北京:清华大学出版社,2007.
[49]SOPC Builder[G],ALTERA公司,2006.5.
[50]林容益.CPU/SOC及外围电路应用设计-基于FPGA/CPLD[M].北京:北京航空航天大学出版社,2006.
[51]Mnl_NIOS2_board_Cyclone_1C20[G].ALTERA公司,2006.5.
[52]高兵,秦俭,陈莉平,唐光荣.NIOSⅡ多核处理器之间通信技术的研究[Z].清华电工电子中心清华-Altera联合实验室.
[53]Avalon Interface Specification[G].ALTERA公司,2005.
[54]Quartus Ⅱ Handbook Volume 4 SOPC Builder[G].ALTERA公司,2006.5.
[2]Hopfield,J.J.,D.Tank.Computing with neural circuits[C].A model Science.1986,233:624- 633.
[3]Nordstrom,T.B.Svensson.Using and designing massively parallel computers for artificial neural networks[C].Journal of Parallel and Distributed Computing.1992,14(3):260-285.
[4]Y.Hirai.Hardware implementations of neural networks[J].Neurocomputing.1993(5):3- 16.
[5]N.Sundarajan,P.Satchandran.Parallel Architectures for Artificial Neural Networks[J].IEE Press.California.1998.
[6]Sund Su Kim,Seul Jung.Hardware Implementation of Real Time Neural Network Controller with a DSP and an FPGA[C].IEEE International Conference on Robotics and Automation.2004,5(4):3161-3165.
[7]杨期鹤,曹年红,陆佶人.基于DSP的BP神经网络的硬件实现[J].信号处理.1998,14(2).
[8]刘丁,万伯任.神经网络硬件研究的现状与趋势[J].计算机应用.1994(1).
[9]王剑,万冬梅,毛宗源.新型联想记忆神经网络的硬件实现研究[J].计算机工程与应用.2003.14.
[10]Cosmin.Hardware neural network-Building Neural Networks with MC431 DSP board[C].8th International Conference on Development and application systems.2006(5).
[11]Adang,Suwandi Ahmad etc.Design and implementation of Parallel Batch-mode Neural Network on Parallel Virtual Machine[C].Proceedings of Industrial Electronics Seminar.1999(10).
[12]Hendrik C A M,Withagen.Neural Networks:Analog VLSI Implementation and Learning Algorithms[D].Ph.D Thesis,Eindhoven,1997.
[13]高丽娜,邱关源.一种连续可调权值CMOS神经网络[J].电子学报.1998,26(2):120-122.
[14]Bernabe Linares-Barranco,et al.A Modular T-Mode Design Approach for Analog Neural Network Hardware Implementations and learning algorithm[J].IEEE Journal of Solid State Circuit.1992,27(5):701-712.
[15]B.M.Wilamowski,J.Binfet,M.O.Kaynak.VLSI Implementation of Neural Networks[]].Int.J.Neural Syst.2000,10(3):191-197.
[16]梁艳,靳东明.基于CMOS模拟电路的径向基函数神经网络[J].半导体学报.2008,29(2).
[17]刘常澎,刘峰,谢学智,庞维珍.可编程细胞神经网络硬件实现及应用研究[J].电子学报.2000,28(4).
[18]Murray,A.F.,et al.Analog Neural VLSI:Issues,Trends and Pulses[J].Artificial Neural Networks.1992:35-43.
[19]Murray,A.F.,et al.Pulse Stream VLSI Neural Networks[J].IEEE Micro.1994,6:29-38.
[20]Fernando Morgado Dias et al.Artificial neural networks:a review of commercial hardware[J].Engineering Applications of Artificial Intelligence(Elsevier Science).2004,17:945-952.
[21]万以华.半导体神经计算机硬件实现研究及在全方位实物识别中的应用[D]:[硕士学位论文].杭州:浙江工业大学,2006,4.
[22]B.E.Boser,E.Sackinger,J.Bromley.An analog neural network processor with programmable topology[C].IEEE J.Solid State Circ.1991,26(12):2017-2025.
[23]B.E.Boser,E.Sackinger,J.Bromley.Hardware Requirements for Neural Network Pattern Classifier[C].IEEE Micro.1992(2):32-40.
[24]王守觉,曹文明.半导体神经计算机的硬件实现及其在连续语音识别中的应用[J].电子学报.2006,34(2):267-271.
[25]Valentina Salapura,Michael Gschwind,et al.A fast FPGA implementation of a general purpose neuron[C].Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications.1994:175-182.
[26]Wolf,D.F.,Romero,R.A.F.,Marques,E.Using Embedded Processors in Hardware Models of Artificial Neural Networks[C].Proceedings of SBAI 2001:78-83.
[27]Ferreira P,Ribeiro P,Antunes A,et al.Artificial neural networks processor:a hardware implementation using a FPGA[C].Proceedings of the 4th International Conference on Field Programmable Logic and Applications.Antwerp.2004:1084-1087.
[28]Wang Q,Yi B,Xie Y,et al.The hardware structure design of perceptron with FPGA implementation[C].Proceedings of IEEE International Conference on Systems,Man and Cybernetics.2003:762-767.
[29]李昂,王沁等.基于FPGA的神经网络硬件实现方法[J].北京科技大学学报.2007,29(1).
[30]魏刚,韩建国.基于FPGA的可重构软测量系统硬件设计[J].仪器仪表用 户.2006,13(4).
[31]James-Roxby,P.,B.A.Blodget.Adapting constant multipliers in a neural network implementation[C].Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines,2000:335-336.
[32]Zhu,J.M.,G.J.Gunther,B.K..Towards an FPGA based reconfigurable computing environment for neural network implementations[C].Proceedings of Ninth International Conference on Artificial Neural Networks.1999,2:661-666.
[33]Xiaoguang LI,Medhat Moussa,Shawki Areibi.Arithmetic formats for implementing Artificial Neural Networks on FPGA[J].Canadian Journal of Electrical and Computer Engineering.2006(1):31-40.
[34]Marchesi,M.,et al.Fast neural networks without multipliers[J].IEEE Transactions on Neural Networks,1993.4(1):53-62.
[35]Reyneri,L.M.Theoretical and implementation aspects of pulse streams:an overview[C].Proceedings of the Seventh International Conference on Microelectronics for Neural,Fuzzy and Bio-Inspired Systems.1999:78-89.
[36]Hikawa,H.A new digital pulse-mode neuron with adjustable activation function[J].IEEE Transactions on Neural Networks.2003.14:236-242.
[37]潘松,黄继业等.SOPC技术实用教程[M].北京:清华大学出版社,2005.
[38]Altera Corp.NIOS Ⅱ Processor Reference Handbook[G].Altera,2005.
[39]Altera Corp.NIOS Ⅱ Software Developer' s Handbook[G].Altera,2005.
[40]Altera Corp.Avlon Interface Specification[G].Altera,2005.
[41]Altera Corp.CycloneⅡ Device Handbook[G].Altera,2005.
[42]Altera Corp.Creating Multiprocessor NIOS Ⅱ System Tutorial[G].Altera,2005.
[43]Altera Corp.Configuration Handbook[G].Altera,2005.
[44]Altera Corp.NIOSⅡ Custom Instruction User Guide[G].Altera,2005.
[45]PicoBlaze 8-bit Embedded Microcontroller User Guide[G].Xilinx,2005.
[46]朱剑英.智能系统非经典数学方法[M].武汉:华中科技大学出版社,2001.
[47]李兰英等.NIOS Ⅱ嵌入式软核SOPC设计原理及应用[M].北京:北京航空航天大学出版社.2006.
[48]郭书军等.嵌入式处理器原理及应用-NIOS系统设计和C程序设计[M].北京:清华大学出版社,2007.
[49]SOPC Builder[G],ALTERA公司,2006.5.
[50]林容益.CPU/SOC及外围电路应用设计-基于FPGA/CPLD[M].北京:北京航空航天大学出版社,2006.
[51]Mnl_NIOS2_board_Cyclone_1C20[G].ALTERA公司,2006.5.
[52]高兵,秦俭,陈莉平,唐光荣.NIOSⅡ多核处理器之间通信技术的研究[Z].清华电工电子中心清华-Altera联合实验室.
[53]Avalon Interface Specification[G].ALTERA公司,2005.
[54]Quartus Ⅱ Handbook Volume 4 SOPC Builder[G].ALTERA公司,2006.5.