嵌入式存储器内建自测试与内建自修复技术研究
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摘要
嵌入式存储器因其高带宽、低功耗、硅面积开销小等优点被广泛应用于片上系统(SoC),预计到2014年,嵌入式存储器在SoC中的硅面积占有率将达到94%。应用嵌入式存储器的系统对可靠性和稳定性的要求较高,因此研究嵌入式存储器的自测试、诊断和自修复技术具有重要的理论意义与实用价值。
本文以嵌入式存储器内建自测试与内建自修复技术为研究内容,以提高片上系统的可靠性与稳定性为目标。涉及到了嵌入式存储器故障的建模、测试与诊断实现以及采用高可靠性内建冗余分析策略实现故障单元的自修复等方面,主要研究成果如下:
为有效定位和识别嵌入式静态随机访问存储器(SRAM)中的各种故障,改进SRAM的设计和生产流程,提出一种有效的March19N(N表示存储器的深度)测试算法。首先把故障注入64×8位的SRAM中;然后将测试算法的读/写操作转化为控制器的控制状态,并设计带诊断支持功能的内建自测试(BIST)模块;最后用该BIST模块测试注入的故障,并对测试数据进行比较与合成,从而实现故障的测试和定位。通过对仿真实验结果的分析,得出了包括固定型故障、开路故障、跳变故障、跳变耦合故障、幂等耦合故障、状态耦合故障和地址译码故障在内的故障字典表,并由此得出各类故障所具有的不同的故障识别标志,最后给出了几种测试算法的时间复杂度、故障诊断率及BIST面积开销。
为有效提高嵌入式SRAM的可靠性,进而确保整个电子系统的可靠运行,通过对嵌入式SRAM故障分布特点的分析,采用了一种改进的存储器架构,采用列块修复与行单元修复相配合的方法,并在此基础了上提出了二维冗余模块存在故障的内建冗余分析(BIRA)策略,该策略高效运用了设置的行修复寄存器与列修复寄存器,极大地提高了故障的修复率。通过16×32位SRAM仿真实验验证了提出的内建冗余分析策略的可行性,有效的确保了系统在冗余模块和主存储器都存在故障的情况下的高可靠运行。
在高可靠性内建冗余分析策略的基础上,实现了内建自修复系统,该系统主要由嵌入式存储器阵列、内建自测试和高可靠性内建冗余分析三个部分组成。最后,通过仿真实验给出了系统的仿真结果图,并给出了内建自修复系统各部分的技术指标及其面积开销。
以上所有电路均用VHDL代码编程实现,在Xilinx的Virtex2系列FPGA上利用Xilinx ISE集成的XST工具综合、布局布线及调用ModelSim SE6.0a软件进行时序仿真、验证。
Embedded memories have been widely applied to the field of system-on-chip (SoC), because there are many advantages regarding embedded memories, e.g., high bandwidth, low consumption and low silicon area overhead, etc. Embedded memories will occupy the largest portion of a SoC (approaching 94% by 2014). Because the system with embedded memories requires high reliability, the techniques of embedded memory self-test and self-repair have significance and practical value.
The main content of this paper is research on built-in self test and built-in self-repair technology for embedded memory, in order to improve the system’s reliability and stability. Related to the embedded memory fault modeling, testing and diagnosis implementation and the using of high-reliability built-in redundancy analysis strategy to achieve self-repair fault unit, the main research results are as follows:
This paper proposes an effective March19N(N represents the address number of memory) test algorithm for an effectively detecting fault locations and identifying variety fault types which produces in the embedded static random access memory (SRAM), consequently improving the design and manufacture process of SRAM. Firstly, faults injection into a 64×8-bit SRAM; Secondly, read and write operations of the algorithm are translated into the states of controller, and then design a built-in self-test (BIST) with diagnostic support module; Finally, using the BIST module test the injection faults, then comparing and synthesizing the test data, in order to achieve faults testing and location. When analyzing simulation results, a fault dictionary is constructed for stuck-at fault, stuck-open fault, transition fault, inversion coupling fault, idempotent coupling fault, state coupling fault and address decoder fault. The fault dictionary shows that faults have different fault signature, finally, time complexity, diagnostic ratio and BIST hardware overhead of several test algorithms is given.
In order to effectively improve the higher reliability of embedded SRAM, thus ensuring the reliability of the entire aerospace electronic systems, through analysis the characteristics of the distribution of faults of embedded SRAM, the method of column block repair and row repair was used on the basis of the improved memory architecture, and built-in redundancy analysis strategy with faults in a 2-D redundancy module was proposed. This strategy efficient use of the row repair register and column repair register in order to improve the repair rate. The simulation experiments for the 64×8-bit SRAM proved the feasibility of BIRA, which ensures reliable operation of the system in the main memory and spare modules exist faults.
The built-in self repair system is given on the based of high-reliability built-in redundancy analysis strategy, the system is made of three mail parts: the embedded memory array, built-in self-test and high reliability built-in redundancy analysis. Finally, the simulation shows the system diagram of the simulation results and gives the technical indicators of the various parts of the built-in self repair system, as well as the hardware overhead.
The whole proposed BIST and BISR circuits were described by VHDL code. They were synthesized, placed and routed by the synthesis tool XST of Xilinx ISE. The simulations were done by Xilinx ISE ordering ModelSim SE6.0a software. The whole designed circuits were verified through Vitex2 FPGA family of Xilinx.
本文以嵌入式存储器内建自测试与内建自修复技术为研究内容,以提高片上系统的可靠性与稳定性为目标。涉及到了嵌入式存储器故障的建模、测试与诊断实现以及采用高可靠性内建冗余分析策略实现故障单元的自修复等方面,主要研究成果如下:
为有效定位和识别嵌入式静态随机访问存储器(SRAM)中的各种故障,改进SRAM的设计和生产流程,提出一种有效的March19N(N表示存储器的深度)测试算法。首先把故障注入64×8位的SRAM中;然后将测试算法的读/写操作转化为控制器的控制状态,并设计带诊断支持功能的内建自测试(BIST)模块;最后用该BIST模块测试注入的故障,并对测试数据进行比较与合成,从而实现故障的测试和定位。通过对仿真实验结果的分析,得出了包括固定型故障、开路故障、跳变故障、跳变耦合故障、幂等耦合故障、状态耦合故障和地址译码故障在内的故障字典表,并由此得出各类故障所具有的不同的故障识别标志,最后给出了几种测试算法的时间复杂度、故障诊断率及BIST面积开销。
为有效提高嵌入式SRAM的可靠性,进而确保整个电子系统的可靠运行,通过对嵌入式SRAM故障分布特点的分析,采用了一种改进的存储器架构,采用列块修复与行单元修复相配合的方法,并在此基础了上提出了二维冗余模块存在故障的内建冗余分析(BIRA)策略,该策略高效运用了设置的行修复寄存器与列修复寄存器,极大地提高了故障的修复率。通过16×32位SRAM仿真实验验证了提出的内建冗余分析策略的可行性,有效的确保了系统在冗余模块和主存储器都存在故障的情况下的高可靠运行。
在高可靠性内建冗余分析策略的基础上,实现了内建自修复系统,该系统主要由嵌入式存储器阵列、内建自测试和高可靠性内建冗余分析三个部分组成。最后,通过仿真实验给出了系统的仿真结果图,并给出了内建自修复系统各部分的技术指标及其面积开销。
以上所有电路均用VHDL代码编程实现,在Xilinx的Virtex2系列FPGA上利用Xilinx ISE集成的XST工具综合、布局布线及调用ModelSim SE6.0a软件进行时序仿真、验证。
Embedded memories have been widely applied to the field of system-on-chip (SoC), because there are many advantages regarding embedded memories, e.g., high bandwidth, low consumption and low silicon area overhead, etc. Embedded memories will occupy the largest portion of a SoC (approaching 94% by 2014). Because the system with embedded memories requires high reliability, the techniques of embedded memory self-test and self-repair have significance and practical value.
The main content of this paper is research on built-in self test and built-in self-repair technology for embedded memory, in order to improve the system’s reliability and stability. Related to the embedded memory fault modeling, testing and diagnosis implementation and the using of high-reliability built-in redundancy analysis strategy to achieve self-repair fault unit, the main research results are as follows:
This paper proposes an effective March19N(N represents the address number of memory) test algorithm for an effectively detecting fault locations and identifying variety fault types which produces in the embedded static random access memory (SRAM), consequently improving the design and manufacture process of SRAM. Firstly, faults injection into a 64×8-bit SRAM; Secondly, read and write operations of the algorithm are translated into the states of controller, and then design a built-in self-test (BIST) with diagnostic support module; Finally, using the BIST module test the injection faults, then comparing and synthesizing the test data, in order to achieve faults testing and location. When analyzing simulation results, a fault dictionary is constructed for stuck-at fault, stuck-open fault, transition fault, inversion coupling fault, idempotent coupling fault, state coupling fault and address decoder fault. The fault dictionary shows that faults have different fault signature, finally, time complexity, diagnostic ratio and BIST hardware overhead of several test algorithms is given.
In order to effectively improve the higher reliability of embedded SRAM, thus ensuring the reliability of the entire aerospace electronic systems, through analysis the characteristics of the distribution of faults of embedded SRAM, the method of column block repair and row repair was used on the basis of the improved memory architecture, and built-in redundancy analysis strategy with faults in a 2-D redundancy module was proposed. This strategy efficient use of the row repair register and column repair register in order to improve the repair rate. The simulation experiments for the 64×8-bit SRAM proved the feasibility of BIRA, which ensures reliable operation of the system in the main memory and spare modules exist faults.
The built-in self repair system is given on the based of high-reliability built-in redundancy analysis strategy, the system is made of three mail parts: the embedded memory array, built-in self-test and high reliability built-in redundancy analysis. Finally, the simulation shows the system diagram of the simulation results and gives the technical indicators of the various parts of the built-in self repair system, as well as the hardware overhead.
The whole proposed BIST and BISR circuits were described by VHDL code. They were synthesized, placed and routed by the synthesis tool XST of Xilinx ISE. The simulations were done by Xilinx ISE ordering ModelSim SE6.0a software. The whole designed circuits were verified through Vitex2 FPGA family of Xilinx.
引文
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[2]陆思安,何乐年,沈海斌.嵌入式存储器内建自测试的原理及实现[J].固体电子学研究与进展,2004,24(2):205-208
[3] David R, Fuentes A, Courtois B. Random patterns testing versus deterministic testing of RAMs[J]. IEEE Transaction on Computers,1989,38(5): 637-650
[4]邹逢兴.计算机应用系统的故障诊断与可靠性技术基础[M].北京,高等教育出版社,1999:5-8, 33-72
[5]袁由光.容错与避错技术及其应用[M].北京,科学出版社,1992:1-15
[6]胡谋.计算机容错技术[M].北京,中国铁道出版社,1995:103-153
[7]郑钧.MOS存储系统及技术[M].北京,科学出版社,1990:140-345
[8] Youngs L, Paramanandam S. Mapping and repairing embedded-memory defects [J]. IEEE on Design & Test of Computers, 1997,14(1):18-24
[9] Y Zorian, S Shoukourian. Embedded-Memory test and repair: infrastructure IP for SoC yield [J]. IEEE Design &Test of Computers,2003,20(3):58~66
[10] Youngs L, Paramanandam S. Mapping and repairing embedded memory Defects[J]. IEEE on Design & Test of Computers, 1997, 14(1):18-24
[11]王达,李华伟,胡瑜等.嵌入式存储器内建自修复技术[J].信息技术快报,2006, 4(1):14-32
[12] Goor van de, A J, Hamdioui. Fault models and tests for two-port memory[J]. Proceedings of 16th IEEE VLSI Test Symposium, Washington DC USA, 1998:401~410
[13] S Hamdioui, Z Al-Ars, AJ van de Goor, etal. Testing static and dynamic faults in random access memories[C].Proceedings of 20th IEEE VLSI Test Symposium (VTS2002), Monterey California USA, 2002:395~400
[14] Hamdioui S, van de Goor, A.J, etal. Detecting intra-word faults in word-oriented memories[C]. Proceedings of 21st VLSI Test Symposium, San Jose, 2003: 241-247
[15] Wang X P, Mehler J N, Meyer F J, et al. Memory Yield and Complexity of Built-in Self-Repair[C]. Proceedings of Reliability and Maintainability Symposium, Alexandria USA, 2005:23-244
[16] Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, et al. March-based RAM diagnosis algorithmsfor stuck-at and coupling faults[C].Proceedings of International Test Conference, Charlotte NC USA, 2001: 758~767
[17] Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu. Testing and diagnosing embedded content addressable memories[C]. Proceedings of 20th IEEE VLSI Test Symposium(VTS2002), Monterey California USA, 2002:389-394
[18] Huang R F, Su C L, Wu C W, et al.Fail pattern identification for memory built-in self-repair[C]. Proceedings of 13th IEEE Asian Test Symposium,2004: 366-371
[19] Xiaogang Du, S M Reddy, Wu-Tung Cheng, et al. At-speed built-in self-repair analyzer for embedded word-oriented memories[C].Proceedings of 17th International Conference on VLSI Design, Mumbai India, 2004:895-900
[20] Shyue-Kung Lu, Yu Ch Ts, Hsu C H, et al. Efficient built-in redundancy analysis for embedded memories with 2-D redundancy[J].IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2006,14(1):34~42
[21] Shyue-Kung Lu, Chih-Hsien Hsu.Fault tolerance techniques for high capacity RAM[J].IEEE Transactions on reliability, 2006,55(2):293-306
[22] Tsu-Wei Tseng, Jin-Fu Li, Da-Ming Chang. A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap[C].Proceedings of International Symposium on Design, Automation and Test,2006:6-10
[23]何蓉晖,李华伟,李晓伟.一款通用CPU嵌入式存储器内建自测试设计[J].同济大学学报(自然科学版),2002,30(10):1204-1208
[24]胡瑜,韩银和,李华伟等.基于双核扫描链平衡的SoC测试调度[J].计算机辅助设计与图形学学报,2005,17(10):2203-2208
[25]胡瑜,韩银和,李晓维.SoC可测性设计与测试技术[J].计算机研究与发展,2005, 42(1):153~162
[26] Allan A, Edenfeld D, Joyner J WH, et al. 2001 international technology roadmap for semiconductors[J]. Computer, 2002, 35(1): 42-35
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[2]陆思安,何乐年,沈海斌.嵌入式存储器内建自测试的原理及实现[J].固体电子学研究与进展,2004,24(2):205-208
[3] David R, Fuentes A, Courtois B. Random patterns testing versus deterministic testing of RAMs[J]. IEEE Transaction on Computers,1989,38(5): 637-650
[4]邹逢兴.计算机应用系统的故障诊断与可靠性技术基础[M].北京,高等教育出版社,1999:5-8, 33-72
[5]袁由光.容错与避错技术及其应用[M].北京,科学出版社,1992:1-15
[6]胡谋.计算机容错技术[M].北京,中国铁道出版社,1995:103-153
[7]郑钧.MOS存储系统及技术[M].北京,科学出版社,1990:140-345
[8] Youngs L, Paramanandam S. Mapping and repairing embedded-memory defects [J]. IEEE on Design & Test of Computers, 1997,14(1):18-24
[9] Y Zorian, S Shoukourian. Embedded-Memory test and repair: infrastructure IP for SoC yield [J]. IEEE Design &Test of Computers,2003,20(3):58~66
[10] Youngs L, Paramanandam S. Mapping and repairing embedded memory Defects[J]. IEEE on Design & Test of Computers, 1997, 14(1):18-24
[11]王达,李华伟,胡瑜等.嵌入式存储器内建自修复技术[J].信息技术快报,2006, 4(1):14-32
[12] Goor van de, A J, Hamdioui. Fault models and tests for two-port memory[J]. Proceedings of 16th IEEE VLSI Test Symposium, Washington DC USA, 1998:401~410
[13] S Hamdioui, Z Al-Ars, AJ van de Goor, etal. Testing static and dynamic faults in random access memories[C].Proceedings of 20th IEEE VLSI Test Symposium (VTS2002), Monterey California USA, 2002:395~400
[14] Hamdioui S, van de Goor, A.J, etal. Detecting intra-word faults in word-oriented memories[C]. Proceedings of 21st VLSI Test Symposium, San Jose, 2003: 241-247
[15] Wang X P, Mehler J N, Meyer F J, et al. Memory Yield and Complexity of Built-in Self-Repair[C]. Proceedings of Reliability and Maintainability Symposium, Alexandria USA, 2005:23-244
[16] Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, et al. March-based RAM diagnosis algorithmsfor stuck-at and coupling faults[C].Proceedings of International Test Conference, Charlotte NC USA, 2001: 758~767
[17] Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu. Testing and diagnosing embedded content addressable memories[C]. Proceedings of 20th IEEE VLSI Test Symposium(VTS2002), Monterey California USA, 2002:389-394
[18] Huang R F, Su C L, Wu C W, et al.Fail pattern identification for memory built-in self-repair[C]. Proceedings of 13th IEEE Asian Test Symposium,2004: 366-371
[19] Xiaogang Du, S M Reddy, Wu-Tung Cheng, et al. At-speed built-in self-repair analyzer for embedded word-oriented memories[C].Proceedings of 17th International Conference on VLSI Design, Mumbai India, 2004:895-900
[20] Shyue-Kung Lu, Yu Ch Ts, Hsu C H, et al. Efficient built-in redundancy analysis for embedded memories with 2-D redundancy[J].IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2006,14(1):34~42
[21] Shyue-Kung Lu, Chih-Hsien Hsu.Fault tolerance techniques for high capacity RAM[J].IEEE Transactions on reliability, 2006,55(2):293-306
[22] Tsu-Wei Tseng, Jin-Fu Li, Da-Ming Chang. A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap[C].Proceedings of International Symposium on Design, Automation and Test,2006:6-10
[23]何蓉晖,李华伟,李晓伟.一款通用CPU嵌入式存储器内建自测试设计[J].同济大学学报(自然科学版),2002,30(10):1204-1208
[24]胡瑜,韩银和,李华伟等.基于双核扫描链平衡的SoC测试调度[J].计算机辅助设计与图形学学报,2005,17(10):2203-2208
[25]胡瑜,韩银和,李晓维.SoC可测性设计与测试技术[J].计算机研究与发展,2005, 42(1):153~162
[26] Allan A, Edenfeld D, Joyner J WH, et al. 2001 international technology roadmap for semiconductors[J]. Computer, 2002, 35(1): 42-35
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