8通道数字信号时序分析实验装置设计
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摘要
为了丰富数字逻辑设计实验教学内容,拓展数字电路实验测试设备功能,基于FPGA设计8通道数字信号时序分析装置。该装置自带8路标准测试信号,通过2个按键实现8位触发字的设置,当8路输入信号符合触发条件时,使能片上RAM存储模块实现对8路数字信号的存储。存储器满时使能DA转换,通过生成两路模拟信号送入数字示波器X、Y通道,利用示波器的X-Y显示模式实现8路数字逻辑信号的显示;具备手动光标测试功能,能够通过LED显示光标所对应的8路逻辑信号。该装置解决了数字电路实验过程中依靠示波器无法同时观测多路逻辑信号的问题,同时能够作为一个工程实践案例引导学生基于FPGA进行数字系统设计。
In order to enrich the teaching content of digital logic design experiment and expand the function of digital circuit experiment testing equipment, an 8-channel digital signal timing analysis device is designed based on FPGA. The device has 8-channel Standard Test signal, and the 8-bit trigger word is set by two keys. When the 8-channel input signal meets the trigger condition, the on-chip RAM is enabled. The storage module realizes the storage of 8 digital signals; when the memory is full, the DA conversion is enabled; two analog signals are generated and sent to the X and Y channels of the digital oscilloscope; the display of 8 digital logic signals is realized by using the X-Y display mode of the oscilloscope; it has the function of manual cursor test and can display the corresponding 8 logos through the LED cursor. Edit the signal. The device solves the problem that the oscilloscope can not simultaneously observe the multi-channel logic signal in the process of digital circuit experiment. At the same time, it can be used as an engineering practice case to guide students to design the digital system based on FPGA.
In order to enrich the teaching content of digital logic design experiment and expand the function of digital circuit experiment testing equipment, an 8-channel digital signal timing analysis device is designed based on FPGA. The device has 8-channel Standard Test signal, and the 8-bit trigger word is set by two keys. When the 8-channel input signal meets the trigger condition, the on-chip RAM is enabled. The storage module realizes the storage of 8 digital signals; when the memory is full, the DA conversion is enabled; two analog signals are generated and sent to the X and Y channels of the digital oscilloscope; the display of 8 digital logic signals is realized by using the X-Y display mode of the oscilloscope; it has the function of manual cursor test and can display the corresponding 8 logos through the LED cursor. Edit the signal. The device solves the problem that the oscilloscope can not simultaneously observe the multi-channel logic signal in the process of digital circuit experiment. At the same time, it can be used as an engineering practice case to guide students to design the digital system based on FPGA.
引文
[1] 党一闻.先进的分布式飞机线缆测试系统设计[J].航空制造技术,2016(4):105-109.
[2] 叶朝辉,华成英,张利伟,等.基于FPGA的SOPC电子系统设计实验研究[J].实验技术与管理,2018,35(3):161-164.
[3] 许可行,吴帅,周晓华.基于嵌入式系统的简易逻辑分析仪设计[J].国外电子测量技术,2017,36(7):77-81.
[4] 刘俊杰,师剑军,周瑞钊,等.便携式逻辑分析仪硬件平台设计[J].火力与指挥控制,2017,42(3):132-136.
[5] 王墨林,戚昊琛,鲁迎春,等.FPGA课程创新型实验教学体系的实践[J].实验科学与技术,2018,16(4):134-139,147.
[6] 张松,李筠.FPGA的模块化设计方法[J].电子测量与仪器学报,2014,28(5):560-565.
[7] 张淑梅.基于ARM+FPGA的高精度数据采集系统设计[J].国外电子测量技术,2014,33(11):62-65.
[8] 谈良,纪凌.基于FPGA的多通道数据采集系统设计与实现[J].电子测量技术,2018,41(5):57-63.
[9] 厉俊男,杨翔瑞,孙志刚.DrawerPipe:基于FPGA的可重构分组处理流水线模型[J].计算机研究与发展,2018,55(4):717-728.
[10] 李进方,许爱强.基于FPGA的脉冲信号参数测量[J].电子测量技术,2018,41(2):119-123.
[11] 石瑞.高精度数字逻辑分析设备的研究[J].机械设计与制造工程,2014,43(5):51-53.
[12] 苏阳,赵英潇,黄睿,等.FPGA的多路数据并行录取和时序资源优化[J].单片机与嵌入式系统应用,2017,17(7):19-22.
[13] 葛桂萍,肖铁军,陈才扣,等.基于FPGA的“计算机组成原理”实践教学的改革[J].实验技术与管理,2018,35(4):12-15.
[14] 邢东洋.传统集成电路与FPGA相结合的数字电子技术综合实验平台的研制[J].科学技术创新,2018(6):173-174.
[15] 陈彦,金燕华,王茜.高校数字逻辑设计课程考核模式的问卷调查与分析[J].教育教学论坛,2015(15):51-52.
[2] 叶朝辉,华成英,张利伟,等.基于FPGA的SOPC电子系统设计实验研究[J].实验技术与管理,2018,35(3):161-164.
[3] 许可行,吴帅,周晓华.基于嵌入式系统的简易逻辑分析仪设计[J].国外电子测量技术,2017,36(7):77-81.
[4] 刘俊杰,师剑军,周瑞钊,等.便携式逻辑分析仪硬件平台设计[J].火力与指挥控制,2017,42(3):132-136.
[5] 王墨林,戚昊琛,鲁迎春,等.FPGA课程创新型实验教学体系的实践[J].实验科学与技术,2018,16(4):134-139,147.
[6] 张松,李筠.FPGA的模块化设计方法[J].电子测量与仪器学报,2014,28(5):560-565.
[7] 张淑梅.基于ARM+FPGA的高精度数据采集系统设计[J].国外电子测量技术,2014,33(11):62-65.
[8] 谈良,纪凌.基于FPGA的多通道数据采集系统设计与实现[J].电子测量技术,2018,41(5):57-63.
[9] 厉俊男,杨翔瑞,孙志刚.DrawerPipe:基于FPGA的可重构分组处理流水线模型[J].计算机研究与发展,2018,55(4):717-728.
[10] 李进方,许爱强.基于FPGA的脉冲信号参数测量[J].电子测量技术,2018,41(2):119-123.
[11] 石瑞.高精度数字逻辑分析设备的研究[J].机械设计与制造工程,2014,43(5):51-53.
[12] 苏阳,赵英潇,黄睿,等.FPGA的多路数据并行录取和时序资源优化[J].单片机与嵌入式系统应用,2017,17(7):19-22.
[13] 葛桂萍,肖铁军,陈才扣,等.基于FPGA的“计算机组成原理”实践教学的改革[J].实验技术与管理,2018,35(4):12-15.
[14] 邢东洋.传统集成电路与FPGA相结合的数字电子技术综合实验平台的研制[J].科学技术创新,2018(6):173-174.
[15] 陈彦,金燕华,王茜.高校数字逻辑设计课程考核模式的问卷调查与分析[J].教育教学论坛,2015(15):51-52.
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