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基于Marx和LTD拓扑的全固态复合模式脉冲源的研制
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  • 英文篇名:The Development of All Solid-State Mixed Pulse Generator Based on Marx and LTD Topologies
  • 作者:王昌金 ; 姚陈果 ; 董守龙 ; 马剑豪 ; 谭坚文
  • 英文作者:Wang Changjin;Yao Chenguo;Dong Shoulong;Ma Jianhao;Tan Jianwen;State Key Laboratory of Power Transmission Equipment & System Security and New Technology Chongqing University;
  • 关键词:脉冲源 ; Marx ; 直线型变压器驱动源 ; 固态开关 ; 现场可编程逻辑门阵列 ; 锁相环
  • 英文关键词:Pulse generator;;Marx;;linear transformer driver;;solid-state switch;;field-programmable gate array;;phase locked loop
  • 中文刊名:DGJS
  • 英文刊名:Transactions of China Electrotechnical Society
  • 机构:输配电装备及系统安全与新技术国家重点实验室(重庆大学);
  • 出版日期:2017-12-04 17:31
  • 出版单位:电工技术学报
  • 年:2018
  • 期:v.33
  • 基金:重庆市杰出青年基金(cstc2014jcyjjq90001);; 国家自然科学基金(51477022);; 重庆市科技计划项目社会事业与民生保障科技创新专项主题专项项目(cstc2015zdcy-ztzx X0003);; 科技部国家重点研发计划(2016YFB0900902)资助
  • 语种:中文;
  • 页:DGJS201813020
  • 页数:9
  • CN:13
  • ISSN:11-2188/TM
  • 分类号:189-197
摘要
针对不同应用领域中负载阻抗的多样性,研制一种基于Marx和直线型变压器驱动源(LTD)拓扑的复合模式脉冲源。该脉冲源包含4个LTD模块,且每个LTD模块由1个3级Marx电路组成。其主要优点是可以降低对隔离电源模块、触发同步性的要求,负载适应能力强,并且可使脉冲装置小型化。首先对该脉冲源拓扑结构和参数进行设计和理论计算,并采用PSpice软件验证其可行性,最后研制复合模式脉冲源的样机并测试其性能。该脉冲源采用MOSFET作为主开关,二极管作为隔离元件,用含锁相环功能的现场可编程门阵列(FPGA)产生控制信号。该脉冲源的输出脉冲参数:幅值为0~8 kV,脉宽为60~160 ns,脉宽步进可达1 ns,重复频率为1 kHz,上升沿约10 ns。通过FPGA产生相移控制信号对该脉冲源的每级进行单独控制,可实现对输出脉冲上升沿和下降沿的灵活调节。脉冲源采用模块化设计,可以通过增加模块数量方便地提高最大输出电压。
        To adapt various load conditions, a mixed pulse generator based on Marx and linear transformer driver(LTD) topologies is designed. It contains four LTD modules, each of which is made by a three-stage Marx circuit. The generator can reduce the demand for the isolated power source and the trigger signals' synchronism, and miniature the device. In this paper, the design and calculation about the generator was proposed, and verified by PSpice software. At last, the prototype of the generator was made and experiments were carried out to test its performance. MOSFETs and diodes are used as the main switch, isolate element, respectively. The control signals were produced by the FPGA which involves phase locked loop. Herein, the output voltage is 0~8 kV, pulsewidth is 60~160 ns with a step size of 1 ns, repetition frequency is 0~1 kHz, and rise time is about 10 ns. The rise and fall time of the output can be adjusted flexibly through FPGA's independent phase shift control to each stage. Moreover, the pulse generator is modularized, with which the maximum output voltage can be easily increased by adding more modules.
引文
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