SM4算法CTR模式的高吞吐率ASIC实现
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摘要
针对同时要求安全性能高和吞吐率高的应用场景,基于支持并行实现的计数器模式SM4算法,提出一种高性能、可扩展的电路结构。该结构分离了控制平面和数据平面,并对数据平面进行了参数化,使得电路性能可依据吞吐率需求进行扩展。通过该结构,既可保障数据的安全性能,又可保证较高的吞吐率。FPGA实现结果显示,单通道设计的吞吐率可达14.647Gbit/s,而资源开销仅为7 423 ALMs。在0.18μm CMOS工艺下进行综合的芯片面积为0.271 mm~2。
Based on SM4 algorithm in Counter (CTR) mode that supports the parallel implementation,a high-performance and scalable architecture is proposed,aiming at meeting the requirements of both high security and high throughput. By separating control plane and data plane,and parameterizing the data plane,the circuit performance can be scaled according to requirement of throughput. Through the proposed architecture,both the security performance and the high throughput can be guaranteed. Results of FPGA implementation demonstrate that the throughput can achieve up to 14.647 Gbit/s of single channel with 7 423 ALMs,and the synthesis results based on 0.18 μm CMOS technology shows that the area of chip is 0.271 mm~2.
Based on SM4 algorithm in Counter (CTR) mode that supports the parallel implementation,a high-performance and scalable architecture is proposed,aiming at meeting the requirements of both high security and high throughput. By separating control plane and data plane,and parameterizing the data plane,the circuit performance can be scaled according to requirement of throughput. Through the proposed architecture,both the security performance and the high throughput can be guaranteed. Results of FPGA implementation demonstrate that the throughput can achieve up to 14.647 Gbit/s of single channel with 7 423 ALMs,and the synthesis results based on 0.18 μm CMOS technology shows that the area of chip is 0.271 mm~2.
引文
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[2]Dworkin M J.Recommendation for Block Cipher Modes of Operation Methods and Techniques[S].National Institute of Standards and Technology,2001,5(6):669-675.
[3]Jin Y,Shen H,You R.Implementation of SMS4 Block Cipher on FPGA[C]//Communications and Networking in China,Chongqing,China,2007:1-4.
[4]结城浩.图解密码技术[M].北京:人民邮电出版社,2015:77-96.
[5]王路,赵鹏,付乔.网络功能虚拟化的关键技术[J].中兴通讯技术,2017,23(2):12-16.
[6]符天枢,李树国.SM4算法CBC模式的高吞吐率ASIC实现[J].微电子学与计算机,2016,33(10):13-18.
[7]王晨光,乔树山,黑勇.低复杂度SM4加密算法IP核设计[J].科学技术与工程,2013,13(2):347-350.
[8]梁浩,乌力吉,张向民.基于复合域的SM4算法的设计与实现[J].微电子学与计算机,2015,32(5):16-20.
[9]朱坤崧,戴紫彬,张立朝,等.面向物联网的SM4算法轻量级实现[J].电子技术应用,2016,42(12):27-30.
[10]刘俊杰,师剑军,张大江,等.SM4算法在无线通信中的硬件实现与应用[J].计算机工程与应用,2016,52(17):118-122.
[11]徐金甫,杨宇航.SM4算法在粗粒度阵列平台的并行化映射[J].电子技术应用,2017,43(4):39-42.
[12]Gao X,Lu E,Xian L,et al.FPGA Implementation of the SMS4Block Cipher in the Chinese WAPI Standard[C]//International Conference on Embedded Software and Systems Symposia.Chengdu,China,2008:104-106.
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