高k+SiO_2栅FD-SOI MOSFET阈值电压和DIBL效应的分析及建模
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摘要
文章提出了高k+SiO_2栅FD-SOI (fully depleted silicon-on-insulator) MOSFET,开发了它的二维亚阈值区前栅表面电势、阈值电压和DIBL (drain induced barrier lowing)效应计算模型.本文根据器件的结构和不同的介电常数,将亚阈值区的FD-SOI MOSFET分成若干个不同的矩形等效源,构建了这个多角形区域的Poisson方程和Laplace方程的二维边界值问题,然后用分离变量法和特征函数展开法求出了模型的二维解.计算结果表明,高k+SiO_2栅能有效地抑制高k介电常数产生的FD-SOI MOSFET阈值电压退化, DIBL效应加重,以及FIBL效应.由于这个模型列出的是线性代数方程组,它的计算开销小,因此这个半解析模型既可以用于FD-SOI MOSFET的模拟和仿真,又可用做电路模拟器的器件模型.
This study aims to propose a gate structure of high k + SiO_2 for a fully depleted silicon-on-Insulator(FD-SOI) MOSFET. We developed a two-dimensional model to calculate its subthreshold surface potential of the front gate, threshold voltage, and drain induced barrier lowering(DIBL) effect. Based on the structure and different dielectric permittivity of FD-SOI MOSFET, the MOSFET of the subthreshold state is divided into several distinct rectangular equivalent sources. Furthermore, two-dimensional(2 D) boundary value problems of Poisson and Laplace equations are built on the polygon region. Then, we use the method of separation of variables and the eigenfunction expansion to solve the 2 D boundary value problems, and obtained their 2 D solutions. Computational results show that the high k + SiO_2 gate can effectively suppress the degradation of FD-SOI MOSFET threshold voltage, the aggravation of DIBL effect, and the FIBL effect, which are caused by the dielectric permittivity of high k. Since the equations of the model are linear equations, their computational cost is minimal so that the model can be used for not only modeling and simulation of FD-SOI MOSFETs but also as a device model of circuit simulators.
This study aims to propose a gate structure of high k + SiO_2 for a fully depleted silicon-on-Insulator(FD-SOI) MOSFET. We developed a two-dimensional model to calculate its subthreshold surface potential of the front gate, threshold voltage, and drain induced barrier lowering(DIBL) effect. Based on the structure and different dielectric permittivity of FD-SOI MOSFET, the MOSFET of the subthreshold state is divided into several distinct rectangular equivalent sources. Furthermore, two-dimensional(2 D) boundary value problems of Poisson and Laplace equations are built on the polygon region. Then, we use the method of separation of variables and the eigenfunction expansion to solve the 2 D boundary value problems, and obtained their 2 D solutions. Computational results show that the high k + SiO_2 gate can effectively suppress the degradation of FD-SOI MOSFET threshold voltage, the aggravation of DIBL effect, and the FIBL effect, which are caused by the dielectric permittivity of high k. Since the equations of the model are linear equations, their computational cost is minimal so that the model can be used for not only modeling and simulation of FD-SOI MOSFETs but also as a device model of circuit simulators.
引文
1 El Dirani H,Fonteneau P,Solaro Y,et al.Sharp-switching band-modulation back-gated devices in advanced FDSOItechnology.Solid-State Electron,2017,128:180-186
2 Shin M,Shi M,Mouis M,et al.In depth characterization of electron transport in 14 nm FD-SOI CMOS devices.Solid-State Electron,2015,112:13-18
3 Xie Q,Xu J,Taur Y.Review and critique of analytic models of MOSFET short-channel effects in subthreshold.IEEETrans Electron Device,2012,59:1569-1579
4 Coquand R,Barraud S,Cass′e M,et al.Scaling of high-k/metal-gate TriGate SOI nanowire transistors down to 10 nm width.Solid-State Electron,2013,88:32-36
5 Makovejev S,Planes N,Haond M,et al.Comparison of self-heating and its effect on analogue performance in 28 nm bulk and FDSOI.Solid-State Electron,2016,115:219-224
6 El Dirani H,Solaro Y,Fonteneau P,et al.A band-modulation device in advanced FDSOI technology:sharp switching characteristics.Solid-State Electron,2016,125:103-110
7 Morvan S,Andrieu F,Barb′e J C,et al.Study of an embedded buried SiGe structure as a mobility booster for fully-depleted SOI MOSFETs at the 10 nm node.Solid-State Electron,2014,98:50-54
8 Meel K,Gopal R,Bhatnagar D.Three-dimensional analytic modelling of front and back gate threshold voltages for small geometry fully depleted SOI MOSFET’s.Solid-State Electron,2011,62:174-184
9 Kumar M J,Chaudhry A.Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs.IEEE Trans Electron Device,2004,51:569-574
10 Mohamad B,Leroux C,Rideau D,et al.Reliable gate stack and substrate parameter extraction based on C-Vmeasurements for 14 nm node FDSOI technology.Solid-State Electron,2017,128:10-16
11 Lo S H,Buchanan D A,Taur Y,et al.Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET’s.IEEE Electron Device Lett,1997,18:209-211
12 Mukhopadhyay B,Biswas A,Basu P K,et al.Modelling of threshold voltage and subthreshold slope of strained-Si MOSFETs including quantum effects.Semicond Sci Technol,2008,23:095017
13 Jayadeva G S,DasGupta A.Analytical approximation for the surface potential in n-channel MOSFETs considering quantum-mechanical effects.IEEE Trans Electron Device,2010,57:1820-1828
14 Kumar A,Tiwari P K.A threshold voltage model of short-channel fully-depleted recessed-source/drain(Re-S/D)UTBSOI MOSFETs including substrate induced surface potential effects.Solid-State Electron,2014,95:52-60
15 Wang M,Ke D M,Xu C X,et al.A 2-D semi-analytical model of parasitic capacitances for MOSFETs with high k gate dielectric in short channel.Solid-State Electron,2014,92:35-39
16 Gan X W,Huang R,Liu X Y,et al.Nano CMOS Devices.Beijing:Science Press,2004[甘学温,黄如,刘晓彦,等.纳米CMOS器件.北京:科学出版社,2004]
17 Yeap G C F,Krishnan S,Lin M R.Fringing-induced barrier lowering(FIBL)in sub-100 nm MOSFETs with high-Kgate dielectrics.Electron Lett,1998,34:1150-1152
18 Cheng B H,Cao M,Rao R,et al.The impact of high-k gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs.IEEE Trans Electron Device,1999,46:1537-1544
19 Hamadeh E A,Niemann D L,Gunther N G,et al.Empirically verified thermodynamic model of gate capacitance and threshold voltage of nanoelectronic MOS devices with applications to HfO2 and ZrO2 gate insulators.IEEE Trans Electron Device,2007,54:2276-2282
20 SILVACO International.ATLAS User’s Manual Device Simulation Software.Santa Clara,2008.40-45
21 Suzuki K,Pidin S.Short-channel single-gate soi mosfet model.IEEE Trans Electron Device,2003,50:1297-1305
22 Joachim H O,Yamaguchi Y,Ishikawa K,et al.Simulation and two-dimensional analytical modeling of subthreshold slope in ultrathin-film SOI MOSFETs down to 0.1μm gate length.IEEE Trans Electron Device,1993,40:1812-1817
23 Rao R,Katti G,Havaldar D S,et al.Unified analytical threshold voltage model for non-uniformly doped dual metal gate fully depleted silicon-on-insulator MOSFETs.Solid-State Electron,2009,53:256-265
24 Chang K M,Wang H P.A simple 2D analytical threshold voltage model for fully depleted short-channel silicon-oninsulator MOSFETs.Semicond Sci Technol,2004,19:1397-1405
25 Li S S.Semiconductor Physical Electronics.2nd ed.Berlin:Springer,2006
26 Liu Z H,Hu C,Huang J H,et al.Threshold voltage model for deep-submicrometer MOSFETs.IEEE Trans Electron Device,1993,40:86-95
27 Mohapatra N R,Desai M P,Narendra S G,et al.Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors.IEEE Trans Electron Device,2003,50:959-966
28 Zeng S R.Fundamentals of Semiconductor Device Physics.Beijing:Peking University Press,2009[曾树容.半导体器件物理基础(第二版).北京:北京大学出版社,2009]
2 Shin M,Shi M,Mouis M,et al.In depth characterization of electron transport in 14 nm FD-SOI CMOS devices.Solid-State Electron,2015,112:13-18
3 Xie Q,Xu J,Taur Y.Review and critique of analytic models of MOSFET short-channel effects in subthreshold.IEEETrans Electron Device,2012,59:1569-1579
4 Coquand R,Barraud S,Cass′e M,et al.Scaling of high-k/metal-gate TriGate SOI nanowire transistors down to 10 nm width.Solid-State Electron,2013,88:32-36
5 Makovejev S,Planes N,Haond M,et al.Comparison of self-heating and its effect on analogue performance in 28 nm bulk and FDSOI.Solid-State Electron,2016,115:219-224
6 El Dirani H,Solaro Y,Fonteneau P,et al.A band-modulation device in advanced FDSOI technology:sharp switching characteristics.Solid-State Electron,2016,125:103-110
7 Morvan S,Andrieu F,Barb′e J C,et al.Study of an embedded buried SiGe structure as a mobility booster for fully-depleted SOI MOSFETs at the 10 nm node.Solid-State Electron,2014,98:50-54
8 Meel K,Gopal R,Bhatnagar D.Three-dimensional analytic modelling of front and back gate threshold voltages for small geometry fully depleted SOI MOSFET’s.Solid-State Electron,2011,62:174-184
9 Kumar M J,Chaudhry A.Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs.IEEE Trans Electron Device,2004,51:569-574
10 Mohamad B,Leroux C,Rideau D,et al.Reliable gate stack and substrate parameter extraction based on C-Vmeasurements for 14 nm node FDSOI technology.Solid-State Electron,2017,128:10-16
11 Lo S H,Buchanan D A,Taur Y,et al.Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET’s.IEEE Electron Device Lett,1997,18:209-211
12 Mukhopadhyay B,Biswas A,Basu P K,et al.Modelling of threshold voltage and subthreshold slope of strained-Si MOSFETs including quantum effects.Semicond Sci Technol,2008,23:095017
13 Jayadeva G S,DasGupta A.Analytical approximation for the surface potential in n-channel MOSFETs considering quantum-mechanical effects.IEEE Trans Electron Device,2010,57:1820-1828
14 Kumar A,Tiwari P K.A threshold voltage model of short-channel fully-depleted recessed-source/drain(Re-S/D)UTBSOI MOSFETs including substrate induced surface potential effects.Solid-State Electron,2014,95:52-60
15 Wang M,Ke D M,Xu C X,et al.A 2-D semi-analytical model of parasitic capacitances for MOSFETs with high k gate dielectric in short channel.Solid-State Electron,2014,92:35-39
16 Gan X W,Huang R,Liu X Y,et al.Nano CMOS Devices.Beijing:Science Press,2004[甘学温,黄如,刘晓彦,等.纳米CMOS器件.北京:科学出版社,2004]
17 Yeap G C F,Krishnan S,Lin M R.Fringing-induced barrier lowering(FIBL)in sub-100 nm MOSFETs with high-Kgate dielectrics.Electron Lett,1998,34:1150-1152
18 Cheng B H,Cao M,Rao R,et al.The impact of high-k gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs.IEEE Trans Electron Device,1999,46:1537-1544
19 Hamadeh E A,Niemann D L,Gunther N G,et al.Empirically verified thermodynamic model of gate capacitance and threshold voltage of nanoelectronic MOS devices with applications to HfO2 and ZrO2 gate insulators.IEEE Trans Electron Device,2007,54:2276-2282
20 SILVACO International.ATLAS User’s Manual Device Simulation Software.Santa Clara,2008.40-45
21 Suzuki K,Pidin S.Short-channel single-gate soi mosfet model.IEEE Trans Electron Device,2003,50:1297-1305
22 Joachim H O,Yamaguchi Y,Ishikawa K,et al.Simulation and two-dimensional analytical modeling of subthreshold slope in ultrathin-film SOI MOSFETs down to 0.1μm gate length.IEEE Trans Electron Device,1993,40:1812-1817
23 Rao R,Katti G,Havaldar D S,et al.Unified analytical threshold voltage model for non-uniformly doped dual metal gate fully depleted silicon-on-insulator MOSFETs.Solid-State Electron,2009,53:256-265
24 Chang K M,Wang H P.A simple 2D analytical threshold voltage model for fully depleted short-channel silicon-oninsulator MOSFETs.Semicond Sci Technol,2004,19:1397-1405
25 Li S S.Semiconductor Physical Electronics.2nd ed.Berlin:Springer,2006
26 Liu Z H,Hu C,Huang J H,et al.Threshold voltage model for deep-submicrometer MOSFETs.IEEE Trans Electron Device,1993,40:86-95
27 Mohapatra N R,Desai M P,Narendra S G,et al.Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors.IEEE Trans Electron Device,2003,50:959-966
28 Zeng S R.Fundamentals of Semiconductor Device Physics.Beijing:Peking University Press,2009[曾树容.半导体器件物理基础(第二版).北京:北京大学出版社,2009]
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