在多核FPGA上实现Office文档口令破解的方法
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摘要
随着计算机技术的发展,微软的Office系列软件已经成为主流的文本编辑软件.找到一种高效的恢复被加密文档的口令的方案具有重要的意义.传统的基于CPU和GPU的破解方法破解速度慢,大大限制了破解的应用.为了提高口令的破解速度,本文提出了基于多核FPGA的设计思想.详细分析了解密Office文档涉及的核心算法SHA1和AES.在全流水线结构下,按照多核并行的设计思想,设计了基于多核FPGA的Office口令破解程序,实现Office口令的高速破解.实验结果表明:在单片四核FPGA上破解Office口令,其破解速度达138600H/s,是普通口令破解软件的62倍,是基于GPU的Hashcat口令破解软件的5倍.基于数据流的设计思想使得流水线上的所有数据块处于高效工作状态,同时多个数据流并行工作.大大提高了破解速度,实现了对Office文档加密密码的快速破解.
With the development of computer technology,Microsoft's OFFICE series software has become the mainstream text editing software. It is important to find an efficient way to recover the password of an encrypted document. The traditional CPU and GPU cracking methods are slow to crack,which greatly limits the application of cracking. In order to improve the speed of password cracking,a design idea based on multi-core FPGA is proposed. This article analyzes in detail the core algorithms SHA1 and AES involved in decrypting Office documents. Under the whole pipeline structure,according to the multi-core parallel design idea,the office password cracking program based on multi-core FPGA is designed to realize the high-speed crack of office password. The experimental results show that the office password is cracked on the single-chip quad-core FPGA,and the crack speed is 138600 H/s,which is 62 times that of the ordinary password cracking software and 5 times that of the GPU-based Hashcat. The data flow-based design makes all the data blocks on the pipeline work in an efficient state,while multiple data streams work in parallel. The crack speed is greatly improved,and it realized the fast decryption of the encrypted password of the office document.
With the development of computer technology,Microsoft's OFFICE series software has become the mainstream text editing software. It is important to find an efficient way to recover the password of an encrypted document. The traditional CPU and GPU cracking methods are slow to crack,which greatly limits the application of cracking. In order to improve the speed of password cracking,a design idea based on multi-core FPGA is proposed. This article analyzes in detail the core algorithms SHA1 and AES involved in decrypting Office documents. Under the whole pipeline structure,according to the multi-core parallel design idea,the office password cracking program based on multi-core FPGA is designed to realize the high-speed crack of office password. The experimental results show that the office password is cracked on the single-chip quad-core FPGA,and the crack speed is 138600 H/s,which is 62 times that of the ordinary password cracking software and 5 times that of the GPU-based Hashcat. The data flow-based design makes all the data blocks on the pipeline work in an efficient state,while multiple data streams work in parallel. The crack speed is greatly improved,and it realized the fast decryption of the encrypted password of the office document.
引文
[1] Li Bin,Zhou Qing-lei,Si Xue-ming. Mimic computing for passw ord recovery[J]. Future Generation Computer Systems,2018,84(1):58-77.
[2] Microsoft Corporation. Compound file binary file format[S]. Microsoft,2012:1-46.
[3] Microsoft Corporation. Office file cryptography structure specification[S]. M icrosoft,2012:1-107.
[4] Li Long-pu,Si Xue-ming,Zhang Zhi-hong,et al. Implementing dictionary-based passw ord recovery for ZIP documents on multiFPGA[J]. Computer Applications&Softw are,2015,(6):292-295.
[5] Yoginder S Dandass. Using FPGAs to parallelize dictionary attacks for passw ord cracking[C]. Haw aii International Conference on System Sciences,IEEE,2008:480-485.
[6] Qiu W,Gong Z,Guo Y,et al. GPU-based high performance passw ord recovery technique for hash functions[J]. Journal of Information Science&Engineering,2016,32(1):97-112.
[7] Wang Wen-gong,Yu Song-lin,Li Yu-feng,et al. Design and implementation of hardw are based on SHA-1[J]. Electronic Design Engineering,2017,25(4):14-17.
[8] Li Lei,Han Wen-bao. Implementation of pipeline structure on FPGA for SHA-1[J]. Computer Science,2011,38(7):58-60.
[9] Kumar V,Pandey P S,Ranjan P. A high-throughput FPGA-based architecture for advanced encryption standard:AES-512 using preciphered lookup table[M]. Intelligent Communication,Control and Devices,2018.
[10] Farooq U,Aslam M F. Comparative analysis of different AES implementation techniques for efficient resource usage and better performance of an FPGA[J]. Journal of King Saud University-Computer and Information Sciences,2016,29(3):1-9.
[11] Tang Jin-yi. Analysis of AES's implementation with FPGA[J].Computer Security,2008,14(6):14-16.
[12] Wong M M,Wong M,Zhang C,et al. Circuit and system design for optimal lightw eight AES encryption on FPGA[J]. Iaeng International Journal of Computer Science,2018,45(1):52-62.
[13] Kim J W,Lee H U,Won Y. Design for high throughput SHA-1hash function on FPGA[C]. Fourth International Conference on Ubiquitous and Future Netw orks,IEEE,2012:403-404.
[14] Lv Hui. Research on crack office file password based on CUDA architecture[D]. Zhengzhou:The PLA Information Engineering University,2014.
[15] Chen Li-juan,Yang Ying,Wang Ji-zhi,et al. Word 2003 document passw ord cracking based on the China supercomputer[M]. Proceedings of the 6th International Asia Conference on Industrial Engineering and M anagement Innovation,Atlantis Press,2016.
[16] Hong Jing-xin,Chen Ze-feng,Hu Jun. Analysis of encryption mechanism in Office 2013[C]. International Conference on AntiCounterfeiting,Security,and Identification,IEEE,2016:29-32.
[17] Hranicky R,Matouek P,Ryavy O,et al. Experimental evaluation of passw ord recovery in encrypted documents[C]. International Conference on Information Systems Security and Privacy,2016:299-306.
[18] Chawla S S,Aggarwal S,Kamal S,et al. FPGA implementation of an optimized 8-bit AES architecture:a masked S-Box and pipelined approach[C]. IEEE International Conference on Electronics,Computing and Communication Technologies,IEEE,2016:1-6.
[19] Ying H M,Kunihiro N. Decryption of frequent password hashes in rainbow tables[C]. International Symposium on Computing&Netw orking,IEEE,2017:655-661.
[4]李龙谱,斯雪明,张志鸿,等.在多FPGA上实现基于字典的ZIP文档口令恢复[J].计算机应用与软件,2015(6):292-295.
[7]王文功,于松林,李玉峰,等.基于SHA-1算法的硬件设计及实现[J].电子设计工程,2017,25(4):14-17.
[8]李磊,韩文报. FPGA上SHA-1算法的流水线结构实现[J].计算机科学,2011,38(7):58-60.
[11]唐金艺. AES算法FPGA实现分析[J].计算机安全,2008,14(6):14-16.
[14]吕辉.基于CUDA架构的Office密文档破解技术研究[D].郑州:解放军信息工程大学,2014.
[2] Microsoft Corporation. Compound file binary file format[S]. Microsoft,2012:1-46.
[3] Microsoft Corporation. Office file cryptography structure specification[S]. M icrosoft,2012:1-107.
[4] Li Long-pu,Si Xue-ming,Zhang Zhi-hong,et al. Implementing dictionary-based passw ord recovery for ZIP documents on multiFPGA[J]. Computer Applications&Softw are,2015,(6):292-295.
[5] Yoginder S Dandass. Using FPGAs to parallelize dictionary attacks for passw ord cracking[C]. Haw aii International Conference on System Sciences,IEEE,2008:480-485.
[6] Qiu W,Gong Z,Guo Y,et al. GPU-based high performance passw ord recovery technique for hash functions[J]. Journal of Information Science&Engineering,2016,32(1):97-112.
[7] Wang Wen-gong,Yu Song-lin,Li Yu-feng,et al. Design and implementation of hardw are based on SHA-1[J]. Electronic Design Engineering,2017,25(4):14-17.
[8] Li Lei,Han Wen-bao. Implementation of pipeline structure on FPGA for SHA-1[J]. Computer Science,2011,38(7):58-60.
[9] Kumar V,Pandey P S,Ranjan P. A high-throughput FPGA-based architecture for advanced encryption standard:AES-512 using preciphered lookup table[M]. Intelligent Communication,Control and Devices,2018.
[10] Farooq U,Aslam M F. Comparative analysis of different AES implementation techniques for efficient resource usage and better performance of an FPGA[J]. Journal of King Saud University-Computer and Information Sciences,2016,29(3):1-9.
[11] Tang Jin-yi. Analysis of AES's implementation with FPGA[J].Computer Security,2008,14(6):14-16.
[12] Wong M M,Wong M,Zhang C,et al. Circuit and system design for optimal lightw eight AES encryption on FPGA[J]. Iaeng International Journal of Computer Science,2018,45(1):52-62.
[13] Kim J W,Lee H U,Won Y. Design for high throughput SHA-1hash function on FPGA[C]. Fourth International Conference on Ubiquitous and Future Netw orks,IEEE,2012:403-404.
[14] Lv Hui. Research on crack office file password based on CUDA architecture[D]. Zhengzhou:The PLA Information Engineering University,2014.
[15] Chen Li-juan,Yang Ying,Wang Ji-zhi,et al. Word 2003 document passw ord cracking based on the China supercomputer[M]. Proceedings of the 6th International Asia Conference on Industrial Engineering and M anagement Innovation,Atlantis Press,2016.
[16] Hong Jing-xin,Chen Ze-feng,Hu Jun. Analysis of encryption mechanism in Office 2013[C]. International Conference on AntiCounterfeiting,Security,and Identification,IEEE,2016:29-32.
[17] Hranicky R,Matouek P,Ryavy O,et al. Experimental evaluation of passw ord recovery in encrypted documents[C]. International Conference on Information Systems Security and Privacy,2016:299-306.
[18] Chawla S S,Aggarwal S,Kamal S,et al. FPGA implementation of an optimized 8-bit AES architecture:a masked S-Box and pipelined approach[C]. IEEE International Conference on Electronics,Computing and Communication Technologies,IEEE,2016:1-6.
[19] Ying H M,Kunihiro N. Decryption of frequent password hashes in rainbow tables[C]. International Symposium on Computing&Netw orking,IEEE,2017:655-661.
[4]李龙谱,斯雪明,张志鸿,等.在多FPGA上实现基于字典的ZIP文档口令恢复[J].计算机应用与软件,2015(6):292-295.
[7]王文功,于松林,李玉峰,等.基于SHA-1算法的硬件设计及实现[J].电子设计工程,2017,25(4):14-17.
[8]李磊,韩文报. FPGA上SHA-1算法的流水线结构实现[J].计算机科学,2011,38(7):58-60.
[11]唐金艺. AES算法FPGA实现分析[J].计算机安全,2008,14(6):14-16.
[14]吕辉.基于CUDA架构的Office密文档破解技术研究[D].郑州:解放军信息工程大学,2014.
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