FPGA硬核处理器系统加速数字电路功能验证的方法
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摘要
为了缩短专用集成电路和片上系统的功能验证周期,该文提出FPGA硬核处理器系统加速数字电路功能验证的方法。所提方法综合软件仿真功能验证和现场可编程门阵列原型验证的优点,利用集成在片上系统现场可编程门阵列器件中的硬核处理器系统作为验证激励发生单元和功能验证覆盖率分析单元,解决了验证速度和灵活性不能统一的问题。与软件仿真验证相比,所提方法可以有效缩短数字电路的功能验证时间;在功能验证效率和验证知识产权可重用方面表现优于现有的FPGA原型验证技术。
In order to reduce the functional verification cycle of application-specific integrated circuits and onchip system, a method for accelerating functional verification with FPGA digital hard processor system is proposed. The proposed method combines the advantages of software simulation function verification and field programmable gate array prototype verification, and uses the hard processor system integrated in the on-chip system field programmable gate array device as the verification excitation generation and the function verification coverage analysis unit. It solves the problem that verification speed and flexibility can not be unified. Compared with software simulation verification, the proposed method can effectively shorten the functional verification time of digital circuits; it is superior to existing FPGA prototyping technology in terms of functional verification efficiency and verification of intellectual property reusability.
In order to reduce the functional verification cycle of application-specific integrated circuits and onchip system, a method for accelerating functional verification with FPGA digital hard processor system is proposed. The proposed method combines the advantages of software simulation function verification and field programmable gate array prototype verification, and uses the hard processor system integrated in the on-chip system field programmable gate array device as the verification excitation generation and the function verification coverage analysis unit. It solves the problem that verification speed and flexibility can not be unified. Compared with software simulation verification, the proposed method can effectively shorten the functional verification time of digital circuits; it is superior to existing FPGA prototyping technology in terms of functional verification efficiency and verification of intellectual property reusability.
引文
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[3]STOTLAND I,SHPAGILEV D,and STARIKOVSKAYAN.UVM based approaches to functional verification of communication controllers of microprocessor systems[C].Proceedings of 2016 IEEE East-West Design&Test Symposium,Yerevan,Armenia,2016:1-4.doi:10.1109/EWDTS.2016.7807695.
[4]HU Zhaohui,PIERRES A,HU Shiqing,et al.Practical and efficient SOC verification flow by reusing IP testcase and testbench[C].Proceedings of 2012 International SoC Design Conference,Jeju Island,South Korea,2012:175-178.doi:10.1109/ISOCC.2012.6407068.
[5]KIM M,KONG J,SUH T,et al.Latch-based FPGAemulation method for design verification:Case study with microprocessor[J].Electronics Letters,2011,47(9):532-533.doi:10.1049/el.2011.0462.
[6]施佺,韩赛飞,黄新明,等.面向全同态加密的有限域FFT算法FPGA设计[J].电子与信息学报,2018,40(1):57-62.doi:10.11999/JEIT170312.SHI Quan,HAN Saifei,HUANG Xinming,et al.Design of finite field FFT for fully homomorphic encryption based on FPGA[J].Journal of Electronics&Information Technology,2018,40(1):57-62.doi:10.11999/JEIT170312.
[7]LI Tiejun,ZHANG Jianmin,and LI Sikun.An FPGA-based random functional verification method for cache[C].Proceedings of the 2013 IEEE 8th International Conference on Networking,Architecture and Storage,Xi'an,China,2013:277-281.doi:10.1109/NAS.2013.44.
[8]GSCHWIND M,SALAPURA V,and MAURER D.FPGA prototyping of a RISC processor core for embedded applications[J].IEEE Transactions on Very Large Scale Integration(VLSI)Systems,2001,9(2):241-250.doi:10 .1109/92.924027.
[9]PODIVINSKY J,CEKAN O,LOJDA J,et al.Functional verification based platform for evaluating fault tolerance properties[J].Microprocessors and Microsystems,2017,52:145-159.doi:10.1016/j.micpro.2017.06.004.
[10]BARNASCONI M,DIETRICH M,EINWICH K,et al.UVM-systemC-AMS framework for system-level verification and validation of automotive use cases[J].IEEE Design&Test,2015,32(6):76-86.doi:10.1109/MDAT.2015.2427260.
[11]IEEE.1800.2-2017 IEEE standard for universal verification methodology language reference manual[S].IEEE,2017.doi:10.1109/IEEESTD.2017.7932212.
[12]CHEN Fulong and SUN Yunxiang.FPGA-based elastic incircuit debugging for complex digital logic design[J].International Journal of Autonomous and Adaptive Communications Systems,2017,10(3):303-319.doi:10.1504/IJAACS.2017.10007621.
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[14]Xilinx Inc.Zynq-7000 all programmable SoC data sheet:Overview[EB/OL].https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#documentation,2018:6.
[15]DUARTE-SáNCHEZ J E,VELASCO-MEDINA J,and MORENO P A.Hardware accelerator for the multifractal analysis of DNA sequences[J].IEEE/ACM Transactions on Computational Biology and Bioinformatics,2018,15(5):1611-1624.doi:10.1109/TCBB.2017.2731339.
[16]ISKANDER Y,PATTERSON C,and CRAVEN S.Highlevel abstractions and modular debugging for FPGA design validation[J].ACM Transactions on Reconfigurable Technology and Systems,2014,7(1):1-22.doi:10.1145/2567662.
[17]SCHAFER B C.Source code error detection in High-level synthesis functional verification[J].IEEE Transactions on Very Large Scale Integration(VLSI)Systems,2016,24(1):301-312.doi:10.1109/TVLSI.2015.2397036.
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