软件无线电数字前端技术的研究和实现
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摘要
随着通信技术的迅猛发展,多种通信体系并存、各种标准竞争激烈、频率资源紧张等问题日益突显。软件无线电(SDR)的出现正是为这些问题的解决提供了现代无线电的方法。目前,个人移动通信设备尚无法在各种标准如(CDMA,GSM,AMPS等)之间自由切换。产品的技术复杂度越来越高,即使经过最严格的测试也难免仍然存在问题,而软件无线电能通过无线下载软件修正疏漏或增添新功能,不断提高服务质量,而这一切对用户来说都是透明的。在软件无线电系统中数字前端(DFE)部分的设计直接关系到整个数字系统接近天线端的距离和程度。在前人研究的基础上,本文针对软件无线电应用中的特点,针对数字前端部分提出了改进算法,有效提高了系统的性能并获得了数字前端部分的硬件消耗和性能之间的平衡,从而使得DFE电路的实现能够更好地适应软件无线电的需求。
DFE中的关键问题仍然是DSP计算能力“瓶颈”问题,即目前DSP处理速度有限,很难用廉价的通用DSP芯片完成DFE的处理任务。对软件接收机而言,中频采样后首先要完成DFE下变频的过程。它主要包括混频、滤波和重采样,这是系统处理中运算量最大的部分,也是最难完成的部分。仅仅使用通用DSP来完成DFE几乎是不能实现的。本文结合目前比较流行的现场可编程门阵列(FPGA)技术进行DFE电路设计,很好地利用了硬件资源的流水线特性,给出了完整的DFE解决方案。
对于传统的硬件设计流程,往往将设计的算法和相应的硬件实现相分割,使得在系统设计之初无法迅速地找到系统可能存在的瓶颈和问题。整个设计需要先将算法的数学描述转化成硬件描述语言(HDL)描述,并在硬件上实现之后才能验证算法的硬件可实现性以及系统资源的占用率。这样,很大程度上使得ASIC设计和算法DSP设计处于脱节的状态。本文使用了MATLAB SIMULINK对相应的算法进行建模,结合了SYSTEM GENERATOR工具以及ISE集成开发环境,使得在系统设计之初就能够实现评估和仿真,并借助强大的数学工具箱来完成浮点原型和定点设计精度的评估。直接在仿真过程中将代码在线下载,使用片上逻辑分析仪来分析当前系统各部分的运行状态。
本文通过系统仿真以及硬件平台验证了软件无线电数字前端实现的有效性,并且在原有下变频各种算法的基础上加以改进系统。提出了一种新的改进算法结构提高了系统NCO的杂散性能,并将算法进行了硬件实现。本文详细地讨论了软件无线电数字前端高效滤波器模块的设计与实现,并综合采用了现有的先进EDA技术使用高效可实现的系统设计建模方法,给出了完整的数字前端处理器设计。最后对本文提出的方法进行了总结和对进一步工作提出了展望。
Along with the rapid development and the expansion of communication technology,many problems including the existence of different communication architecture,the compition between various standards and the usage of frequency resources become more and more urgent.Software Defined Radio(SDR)provides the modem solution for above problems.The SDR can offer updated functionalities and improve the communication services which are transparent to the customers.The design technique of the Digital Front End(DFE)part in SDR is critical,as which is able to influence the distance between the digital part and the antenna.
Based on anterior theories and research results,this thesis made some improvements to the algorithm of DFE part which enhances the system performance and makes it more fit for the SDR application.
The critical problem of the DFE is the Digital Signal Processing(DSP)bottleneck, it is hard to use an inexpensive general DSP processor to finish the rough task,which is to blame for the low MIPS performance.With respect to a SDR DFE receiver,the downlink path consists of mixer,filter,multirate processing and etc,which are the most resource consuming and intense computing part of the design.General DSP processor can not afford such high volume data throughput.Instead,all the designs in this thesis are based on Field Programmable Gate Array(FPGA)technology,which is born with parallel pipelining feature and other utilities.An integrated DFE downlink design is implemented.
With respect to the conventional design flow of the FPGA based applications, there is always a gap between the design of the algorithm and the implementing of the corresponding fixed point design.This gap might blind the system designer and conceal some glitches or bottlenecks inside the system.After the algorithm is ready, the mathematic description should be converted to the Hardware Discription Language(HDL)first and then the consumption of the resources and the implementing performance can be accessible after the hardware simulation.In this thesis,MATLAB SIMULINK environment is employed to finish the algorithm and system modeling,with the help of powerful toolboxes and hardware mapped simulink blocks,immediate floating and fixed point results can be evaluated at the system and algorithm level,the corresponding codes can be generated and implemented to the real hardware thanks to the System generator and ISE development tools.Moreover, on chip block status can be read from the embedded logical analyzer and the hardware results could be evaluated on the desktop.
In sum,in this thesis,improvements have been made to enhance the CORDIC algorithm and provide a better performance NCO in DFE,which has been implemented in FPGA hardware.After that,the low cost multirate fiters have been discussed and corresponding modeling and implementing are also proposed.Besides, an integrated DFE processor which consists of improved NCO,multirate filters and gain controller is designed,simulated and implemented.Moreover,all the designs should thanks to the advanced EDA based design flow.Finally,a conclusion and future view of the related work have been made at the end of the thesis.
DFE中的关键问题仍然是DSP计算能力“瓶颈”问题,即目前DSP处理速度有限,很难用廉价的通用DSP芯片完成DFE的处理任务。对软件接收机而言,中频采样后首先要完成DFE下变频的过程。它主要包括混频、滤波和重采样,这是系统处理中运算量最大的部分,也是最难完成的部分。仅仅使用通用DSP来完成DFE几乎是不能实现的。本文结合目前比较流行的现场可编程门阵列(FPGA)技术进行DFE电路设计,很好地利用了硬件资源的流水线特性,给出了完整的DFE解决方案。
对于传统的硬件设计流程,往往将设计的算法和相应的硬件实现相分割,使得在系统设计之初无法迅速地找到系统可能存在的瓶颈和问题。整个设计需要先将算法的数学描述转化成硬件描述语言(HDL)描述,并在硬件上实现之后才能验证算法的硬件可实现性以及系统资源的占用率。这样,很大程度上使得ASIC设计和算法DSP设计处于脱节的状态。本文使用了MATLAB SIMULINK对相应的算法进行建模,结合了SYSTEM GENERATOR工具以及ISE集成开发环境,使得在系统设计之初就能够实现评估和仿真,并借助强大的数学工具箱来完成浮点原型和定点设计精度的评估。直接在仿真过程中将代码在线下载,使用片上逻辑分析仪来分析当前系统各部分的运行状态。
本文通过系统仿真以及硬件平台验证了软件无线电数字前端实现的有效性,并且在原有下变频各种算法的基础上加以改进系统。提出了一种新的改进算法结构提高了系统NCO的杂散性能,并将算法进行了硬件实现。本文详细地讨论了软件无线电数字前端高效滤波器模块的设计与实现,并综合采用了现有的先进EDA技术使用高效可实现的系统设计建模方法,给出了完整的数字前端处理器设计。最后对本文提出的方法进行了总结和对进一步工作提出了展望。
Along with the rapid development and the expansion of communication technology,many problems including the existence of different communication architecture,the compition between various standards and the usage of frequency resources become more and more urgent.Software Defined Radio(SDR)provides the modem solution for above problems.The SDR can offer updated functionalities and improve the communication services which are transparent to the customers.The design technique of the Digital Front End(DFE)part in SDR is critical,as which is able to influence the distance between the digital part and the antenna.
Based on anterior theories and research results,this thesis made some improvements to the algorithm of DFE part which enhances the system performance and makes it more fit for the SDR application.
The critical problem of the DFE is the Digital Signal Processing(DSP)bottleneck, it is hard to use an inexpensive general DSP processor to finish the rough task,which is to blame for the low MIPS performance.With respect to a SDR DFE receiver,the downlink path consists of mixer,filter,multirate processing and etc,which are the most resource consuming and intense computing part of the design.General DSP processor can not afford such high volume data throughput.Instead,all the designs in this thesis are based on Field Programmable Gate Array(FPGA)technology,which is born with parallel pipelining feature and other utilities.An integrated DFE downlink design is implemented.
With respect to the conventional design flow of the FPGA based applications, there is always a gap between the design of the algorithm and the implementing of the corresponding fixed point design.This gap might blind the system designer and conceal some glitches or bottlenecks inside the system.After the algorithm is ready, the mathematic description should be converted to the Hardware Discription Language(HDL)first and then the consumption of the resources and the implementing performance can be accessible after the hardware simulation.In this thesis,MATLAB SIMULINK environment is employed to finish the algorithm and system modeling,with the help of powerful toolboxes and hardware mapped simulink blocks,immediate floating and fixed point results can be evaluated at the system and algorithm level,the corresponding codes can be generated and implemented to the real hardware thanks to the System generator and ISE development tools.Moreover, on chip block status can be read from the embedded logical analyzer and the hardware results could be evaluated on the desktop.
In sum,in this thesis,improvements have been made to enhance the CORDIC algorithm and provide a better performance NCO in DFE,which has been implemented in FPGA hardware.After that,the low cost multirate fiters have been discussed and corresponding modeling and implementing are also proposed.Besides, an integrated DFE processor which consists of improved NCO,multirate filters and gain controller is designed,simulated and implemented.Moreover,all the designs should thanks to the advanced EDA based design flow.Finally,a conclusion and future view of the related work have been made at the end of the thesis.
引文
[1]Mitola,J.Software radios-survey,critical evaluation and future directions.Telesystems Conference,1992,13:15-23.
[2]Mitola,J.The Software Radio Architecture.IEEE Communications Magazine,1995,33(5):26-38
[3]Enrico Buracchini.The Software Radio Concept.IEEE Communications Magazine,2000,38(9):138-143.
[4]W.Tuttlebee.The Impact of Software Radio.SW Wksp,Brusels,1997:203-221.
[5]Joseph Mitola Ⅲ.Software Radio Architecture:Object Oriented Approaches to Wireless Systems Engineering.John Wiley and Sons,2000.
[6]Svensson,C.Software Defined Radio-Vision or Reality.Nov.2006:149 Norchip Conference,2006.
[7]Software Radio:A Modern Approach to Radio Engineering.Prentice Hall.May 2002
[8]G.Hueber.Concept of a SDR Compliant Receive Digital-Front-End for Cellular Terminals.Proceeding(464)Networks and Communication Systems-2005
[9]Valkama M,Pirskanen J,Renfors M.Signal processing challenges for applying software radio principles in future wireless terminals:an overview.International journal of communication systems.2002.15(2):741-769
[10]姜宇柏,游思晴 软件无线电原理与工程应用 北京:机械工业出版社 2007.1.
[11]Texas Instruments' Software Defined Radio Development Platform.Focus.ti.com/SDRprs
[12]Jen-Chuan Chih and Sau-Gee Chen,"A Fast CORDIC Algorithm Based On a Novel Angle Recording Scheme," ISCAS 2000-IEEE International Symposium on Circuit and Systems,May 28-31,2000.
[13]Laddomada M.Reconfiguration issues of future mobile software radio platforms.Wireless communications & mobile computer.2002.10(2):815-826.
[14]陈勇 基于FPGA实现高速专用数字下变频 成都:电子科技大学,2005:10-44.
[15]James E.Gunn,Kenneth S.Barron,Willianm Ruczczyk.A low-Power DSP Core-based Software Radio Architecture,IEEE Journal on Selected Areas in Communications.1999.17(4):601-602
[16]Morelos Zaragonza R,Haruyama S,Abe M,etal.A software radio receiver with direct conversion and its digital processing.IEICE Transactions on Communications.2002:2741-2749
[17]Uwe Meyer-Baese.数字信号处理的FPGA实现[M].北京:清华大学出版社,2003
[18]刘必虎 数字逻辑电路 北京:科学出版社,1999
[19]周明德 微型计算机系统原理及应用 北京 清华大学出版社 2001
[20]刘树棠 数字信号处理MATLAB版 西安交通大学出版社 2008.1
[21]JOHN G.PROAKIS,DIMITRIS G.MANOLAKIS,DIGITAL SIGNAL PROCESSING:PRINCIPLES,ALGORITHMS,AND APPLICATIONS.Prentice Hall 2004.9
[22]ROBERTO CRISTI,MODERN DIGITAL SIGNAL PROCESSING.Prentice-Hall 2005.5
[23]SANJITK.MITRA,DIGITAL SIGNAL PROCESSING:A COMPUTER-BASED APPROACH.电子工业出版社 2006.6
[24]WAYNE WOLF,FPGA-BASED SYSTEM DESIGN.机械工业出版社 2006.5
[25]COFER,R.C.HARDING,BENJAMIN F.RAPID SYSTEM PROTOTYPING WITH FPGAS.Butterworth-Heinemann.2005.7
[26]www.xilinx.com Virtex-Ⅱ Pro/Virtex-Ⅱ Pro X Complete Data Sheet.2007.11
[27]C.RICHARD JOHNSON:WILLIAM A.SETHARES.TELECOMMUNICATIONS BREAKDOWN:CONCEPTS OF COMMUNICATION TRANSMITTED VIA SOFTWARE-DEFINED RADIO.机械工业出版社 2008.1
[28]张睿,李维英,李建东,带通采样技术在软件接收机中的应用。 西安电子科技大学学报(自然科学版)。2000(6):326-329
[29]陶然 多抽样率数字信号处理理论及其应用。清华大学出版社 2007.4.
[30]J.E.Volder,"The CORDIC trigonometric computing technique," IRE Trans.Electronic Comput.,vol.EC-8,pp.330-334,1959.
[31]Y.H.Hu,"CORDIC-based VLSI architectures for digital signal processing," IEEE Signal Processing Magazine,pp.16-35,July 1992.
[32]Ray Andraka.A survey of CORDIC algorithms for FPGA based computers.Proceedings of the 1998ACM/SIGDA 1998:191-200
[33]http://www.xilinx.com/support/sw_manuals/sysgen_ug.pdf 2007.Mar
[34]www.mathworks.com/access/helpdesk/help/toolbox/slhdlcoder/2007.June
[35]Shen-Fu Hsiao,Yu-Hen Hu,Tso-Bing Juang.A Memory-Efficient and High-speed Sine/Cosine Generator Based On Parallel CORDIC Rotations.IEEE Digital Processing Letters,VOL.11,No,2,2004.2
[36]李涛,韩月秋。 基于流水线CORDIC算法的三角函数发生器。 电子技术应用。 1999(6):52-53
[37]王军,田忠。 基于CORDIC算法的数字下变频器。现代电子技术。2004,(13):94-96
[38]李岩,汪海明,郭士德等。CORDIC算法在DSP算法硬件实现中的应用进展。现代电子技术。2002,6:85-89
[39]J.E.Voider,"The birth of CORDIC," J.VLSI Signal Processing,vol.25,pp.101-105,June 2000.
[40]J.S.Walther,"The story of unified CORDIC," J.VLSI Signal Processing,vol.25,pp.107-112,June 2000.
[41]J.-H.Kwak et al.,"High-speed CORDIC based on an overlapped architecture and a novel -prediction method," J.VLSI Signal Processing,vol.25,pp.167-177,June 2000.
[42]Cheng-Shing Wu,An-Yeu Wu.Modified Vector Rotational CORDIC(MVR-CORDIC)Algorithm and Architecture.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-Ⅱ:ANALOG AND DIGITAL SIGNAL PROCESSING,VOL.48,NO.6,JUNE 2001
[43]An-Yeu Wu,Cheng-Shing Wu.A Unified View for Vector Rotational CORDIC Algorithms and Architectures Based on Angle Quantization Approach.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-Ⅰ:FUNDAMENTAL THEORY AND APPLICATIONS,VOL.49,NO.10,OCTOBER 2002
[44]Cheng-Shing Wu,An-Yeu Wu.A Novel Rotational VLSI Architecture based on Extended Elementary Angle Set CORDIC Algorithm ASICs,2000.AP-ASIC 2000.Proceedings of the Second IEEE Asia Pacific Conference on 2000
[45]Cheng-Shing Wu An-Yeu Wu.A Novel Trellis-Based Searching Scheme for EEAS-Based CORDIC Algorithm.Acoustics,Speech,and Signal Processing,2001.Proceedings.(ICASSP '01).2001 IEEE
[46]C.H.Lin,A.Y.Wu,"Mixed-scaling-rotation CORDIC(MSR-CORDIC)algorithm and architecture for highperformance vector rotational DSP applications," IEEE Trans.Circuits and Systems Part-Ⅰ:Fundamental Theory and Applications,Vol.52,No.11,pp.2385-2396,Nov.2005.International Conference on 2001
[47]Fred Harris and Bill McKnight,"Error Feedback Loop Linearizes Direct Digital Synthesizers",29-th Asilomar Conference on Signals,Systems,and Computers,pp.98-102,Pacific Grove,CA,30-Oct.to 2-Nov.1995
[48]Hentschel T.,Fettweis G.Sample rate conversion for software radio.IEEE Commun.Mag,2000,9:142-150.
[49]Hogenauer,E.An economical class of digital filters for decimation and interpolation.Acoustics,Speech,and Signal Processing[see also IEEE Transactions on Signal Processing],IEEE Transactions on 1981
[50]fredric j harris Multirate Signal Processing for Communication Systems.Prentice Hall May 2004
[51]http://www.xilinx.com/publications/matrix/DSP_selection_guide March 2008
[2]Mitola,J.The Software Radio Architecture.IEEE Communications Magazine,1995,33(5):26-38
[3]Enrico Buracchini.The Software Radio Concept.IEEE Communications Magazine,2000,38(9):138-143.
[4]W.Tuttlebee.The Impact of Software Radio.SW Wksp,Brusels,1997:203-221.
[5]Joseph Mitola Ⅲ.Software Radio Architecture:Object Oriented Approaches to Wireless Systems Engineering.John Wiley and Sons,2000.
[6]Svensson,C.Software Defined Radio-Vision or Reality.Nov.2006:149 Norchip Conference,2006.
[7]Software Radio:A Modern Approach to Radio Engineering.Prentice Hall.May 2002
[8]G.Hueber.Concept of a SDR Compliant Receive Digital-Front-End for Cellular Terminals.Proceeding(464)Networks and Communication Systems-2005
[9]Valkama M,Pirskanen J,Renfors M.Signal processing challenges for applying software radio principles in future wireless terminals:an overview.International journal of communication systems.2002.15(2):741-769
[10]姜宇柏,游思晴 软件无线电原理与工程应用 北京:机械工业出版社 2007.1.
[11]Texas Instruments' Software Defined Radio Development Platform.Focus.ti.com/SDRprs
[12]Jen-Chuan Chih and Sau-Gee Chen,"A Fast CORDIC Algorithm Based On a Novel Angle Recording Scheme," ISCAS 2000-IEEE International Symposium on Circuit and Systems,May 28-31,2000.
[13]Laddomada M.Reconfiguration issues of future mobile software radio platforms.Wireless communications & mobile computer.2002.10(2):815-826.
[14]陈勇 基于FPGA实现高速专用数字下变频 成都:电子科技大学,2005:10-44.
[15]James E.Gunn,Kenneth S.Barron,Willianm Ruczczyk.A low-Power DSP Core-based Software Radio Architecture,IEEE Journal on Selected Areas in Communications.1999.17(4):601-602
[16]Morelos Zaragonza R,Haruyama S,Abe M,etal.A software radio receiver with direct conversion and its digital processing.IEICE Transactions on Communications.2002:2741-2749
[17]Uwe Meyer-Baese.数字信号处理的FPGA实现[M].北京:清华大学出版社,2003
[18]刘必虎 数字逻辑电路 北京:科学出版社,1999
[19]周明德 微型计算机系统原理及应用 北京 清华大学出版社 2001
[20]刘树棠 数字信号处理MATLAB版 西安交通大学出版社 2008.1
[21]JOHN G.PROAKIS,DIMITRIS G.MANOLAKIS,DIGITAL SIGNAL PROCESSING:PRINCIPLES,ALGORITHMS,AND APPLICATIONS.Prentice Hall 2004.9
[22]ROBERTO CRISTI,MODERN DIGITAL SIGNAL PROCESSING.Prentice-Hall 2005.5
[23]SANJITK.MITRA,DIGITAL SIGNAL PROCESSING:A COMPUTER-BASED APPROACH.电子工业出版社 2006.6
[24]WAYNE WOLF,FPGA-BASED SYSTEM DESIGN.机械工业出版社 2006.5
[25]COFER,R.C.HARDING,BENJAMIN F.RAPID SYSTEM PROTOTYPING WITH FPGAS.Butterworth-Heinemann.2005.7
[26]www.xilinx.com Virtex-Ⅱ Pro/Virtex-Ⅱ Pro X Complete Data Sheet.2007.11
[27]C.RICHARD JOHNSON:WILLIAM A.SETHARES.TELECOMMUNICATIONS BREAKDOWN:CONCEPTS OF COMMUNICATION TRANSMITTED VIA SOFTWARE-DEFINED RADIO.机械工业出版社 2008.1
[28]张睿,李维英,李建东,带通采样技术在软件接收机中的应用。 西安电子科技大学学报(自然科学版)。2000(6):326-329
[29]陶然 多抽样率数字信号处理理论及其应用。清华大学出版社 2007.4.
[30]J.E.Volder,"The CORDIC trigonometric computing technique," IRE Trans.Electronic Comput.,vol.EC-8,pp.330-334,1959.
[31]Y.H.Hu,"CORDIC-based VLSI architectures for digital signal processing," IEEE Signal Processing Magazine,pp.16-35,July 1992.
[32]Ray Andraka.A survey of CORDIC algorithms for FPGA based computers.Proceedings of the 1998ACM/SIGDA 1998:191-200
[33]http://www.xilinx.com/support/sw_manuals/sysgen_ug.pdf 2007.Mar
[34]www.mathworks.com/access/helpdesk/help/toolbox/slhdlcoder/2007.June
[35]Shen-Fu Hsiao,Yu-Hen Hu,Tso-Bing Juang.A Memory-Efficient and High-speed Sine/Cosine Generator Based On Parallel CORDIC Rotations.IEEE Digital Processing Letters,VOL.11,No,2,2004.2
[36]李涛,韩月秋。 基于流水线CORDIC算法的三角函数发生器。 电子技术应用。 1999(6):52-53
[37]王军,田忠。 基于CORDIC算法的数字下变频器。现代电子技术。2004,(13):94-96
[38]李岩,汪海明,郭士德等。CORDIC算法在DSP算法硬件实现中的应用进展。现代电子技术。2002,6:85-89
[39]J.E.Voider,"The birth of CORDIC," J.VLSI Signal Processing,vol.25,pp.101-105,June 2000.
[40]J.S.Walther,"The story of unified CORDIC," J.VLSI Signal Processing,vol.25,pp.107-112,June 2000.
[41]J.-H.Kwak et al.,"High-speed CORDIC based on an overlapped architecture and a novel -prediction method," J.VLSI Signal Processing,vol.25,pp.167-177,June 2000.
[42]Cheng-Shing Wu,An-Yeu Wu.Modified Vector Rotational CORDIC(MVR-CORDIC)Algorithm and Architecture.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-Ⅱ:ANALOG AND DIGITAL SIGNAL PROCESSING,VOL.48,NO.6,JUNE 2001
[43]An-Yeu Wu,Cheng-Shing Wu.A Unified View for Vector Rotational CORDIC Algorithms and Architectures Based on Angle Quantization Approach.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-Ⅰ:FUNDAMENTAL THEORY AND APPLICATIONS,VOL.49,NO.10,OCTOBER 2002
[44]Cheng-Shing Wu,An-Yeu Wu.A Novel Rotational VLSI Architecture based on Extended Elementary Angle Set CORDIC Algorithm ASICs,2000.AP-ASIC 2000.Proceedings of the Second IEEE Asia Pacific Conference on 2000
[45]Cheng-Shing Wu An-Yeu Wu.A Novel Trellis-Based Searching Scheme for EEAS-Based CORDIC Algorithm.Acoustics,Speech,and Signal Processing,2001.Proceedings.(ICASSP '01).2001 IEEE
[46]C.H.Lin,A.Y.Wu,"Mixed-scaling-rotation CORDIC(MSR-CORDIC)algorithm and architecture for highperformance vector rotational DSP applications," IEEE Trans.Circuits and Systems Part-Ⅰ:Fundamental Theory and Applications,Vol.52,No.11,pp.2385-2396,Nov.2005.International Conference on 2001
[47]Fred Harris and Bill McKnight,"Error Feedback Loop Linearizes Direct Digital Synthesizers",29-th Asilomar Conference on Signals,Systems,and Computers,pp.98-102,Pacific Grove,CA,30-Oct.to 2-Nov.1995
[48]Hentschel T.,Fettweis G.Sample rate conversion for software radio.IEEE Commun.Mag,2000,9:142-150.
[49]Hogenauer,E.An economical class of digital filters for decimation and interpolation.Acoustics,Speech,and Signal Processing[see also IEEE Transactions on Signal Processing],IEEE Transactions on 1981
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