面向应用的指令集处理器关键技术研究
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摘要
媒体处理、软件无线电等领域中,应用标准不断演进、算法的复杂度日益增加。同时,人们不断要求媒体和通信技术提供更高的服务质量。这些因素使得应用计算复杂度的增长速度远超过处理器性能提升的速度。处理器必须在给定的资源约束下和约定的时间内完成大量的数据计算。受寄存器文件面积、延时和功耗的影响,及指令集结构、指令编码方式和指令执行控制逻辑的限制,传统的超长指令字或超标量单处理器的可扩展性和功耗效率非常有限。同时由于应用中单线程的指令级并行度有限,单处理器的性能已难以再随片上可用资源的增加而增加。
过去10年里,片上多处理器(Multiprocessor System-on-Chip,MPSoC)证明是进一步提升处理器性能和功耗效率的有效方式之一。MPSoC通过将片上资源划分到多个处理器核中实现了多任务的并发运行,有利于减小处理器核的复杂度、降低MPSoC系统的工作频率、提高MPSoC系统的功耗效率。但串行编写的应用程序使得应用难以快速、高效地映射到MPSoC上。同时MPSoC的片上通信对处理器的性能、面积和功耗均产生一定的开销。这些因素使得MPSoC的性能并没有像预期的那样随集成电路技术带来的片上可用资源的增加而线性增加。
单处理器解决方案具有应用编程简单、资源通信开销小等优点。同时,基于传统处理器核对指令集、存储结构、通信协议等进行扩展构建面向应用的处理器证明是一种提升功耗效率的有效方式。因此,在MPSoC虽已成为处理器发展主流的时代有必要重新审视单处理器解决方案,找出限制单处理器的性能和功耗效率的关键因素,考虑单处理器满足数据计算密集型复杂应用的计算需求的可能。本文通过分析应用及其执行特征试图找出单处理器的根本缺陷,并在指令集定制、指令执行控制方式、可扩展指令编码、面向应用的处理器结构方面展开研究,提出了提升单处理器性能和功耗效率的相关技术。本文的研究内容和主要贡献如下:
1)分析了两种典型应用及其在VLIW结构处理器上的运行情况,总结了单处理器在处理计算密集型复杂应用方面的不足。通过分析发现,两种典型应用在任务级、循环级、基本块级和指令级多个层次均存在不同程度的并行性,且核心算法的计算模式相对固定。但是,传统处理器的指令执行控制方式和指令编码方式限制了处理器的可扩展性;传统的RISC处理器的指令集过于精简,不利于处理器的性能和功耗效率的提升;传统的充分考虑控制相关、数据相关和资源相关等信息的指令调度方式可扩展性差,不利于充分发挥处理器中可用资源的效能。
2)提出了一种快速的扩展指令集自动产生方法。该方法首先分析应用、获取应用中常用的算术逻辑操作,并以这些操作为中心采用加窗、步进等方式逐步增加扩展指令的复杂度,在保证每个步骤的输出均是局部最优结果的同时控制可算法复杂度。该方法不仅可以有效开发设计空间、产生高效的扩展指令,而且算法复杂度与典型操作的数量成正比,与以每个典型操作为中心进行的平均搜索步骤成正比,从而使得算法复杂度随应用复杂度的增加成线性增加。
3)提出了一种新的指令资源压缩方法。该方法首先找出扩展指令的关键路径并将指令的数据流图分割成多条件路径,然后将一条指令的路径与其它所有指令的路径一一匹对找出路径的最大公共等价子串,再以最大公共等价子串为索引压缩所有路径,从而保证了指令间的资源充分共享。同时,该方法允许对指令的数据流图进行修改,在路径中插入延迟和资源开销小的简单操作使路径或路径的一部分的数据流图与其它路径或者其它路径的一部分的数据流图等同,从而减小了插入的多路选择器的数量,减小了多路选择器产生的面积、延时开销。
4)提出了一种软/硬件协同的指令编码方法,旨在不显著增加代码尺寸的情况下消除指令编码对处理器的可扩展性的限制,同时保持原处理器的指令字长、指令集结构、硬件解码结构和编译调度算法不变。该方法基于簇型处理器(Clustered Processors)通过将派发到相同簇中的功能单元上执行的指令组合在一个指令包内,将包内指令的公共信息抽取出来以指令包头的形式插入包中,减小了指令字内需要编码的信息量,增加了固定长指令字的编码空间。同时,该方法对公共信息的类型以及包头指令的数量没有限制,从而提高了该方法的可扩展性。
5)提出了一种集中式和分布式相结合的指令执行控制机制,即取指、译码和流出仍采用集中控制方式,指令的执行和写回采用分布式控制方式。这种机制将指令的译码和流出由原来的指令级转变成指令包级,简化了指令流出的复杂度。同时,该机制将指令执行过程中的取数、执行、写回三个环节的控制过程交给功能单元和分布式寄存器文件,不仅简化了控制逻辑的复杂度而且实现了控制机制的可扩展性。此外,该机制允许产生数据的指令输出一旦有效后马上就能被消费数据的指令使用,提高了处理器开发数据局部性的能力。
6 )基于一种可扩展的簇型处理器提出了可以支持复杂指令的ASIP(Application-Specific Instruction-set Processor)结构。该ASIP的基本结构中的功能单元、寄存器文件被划分到多个簇中,各个簇可以自行管理派发到簇内的指令的执行并通过可扩展的操作数传递网实现簇间通信。因而,向基本结构中添加包含扩展功能单元的扩展簇时不影响其它的结构和资源分配,从而减小了ASIP的设计复杂度。同时,扩展功能单元允许扩展指令具有最多6个输入操作数和最多2个输出操作数,允许扩展指令具有更高的复杂度,极大地拓展了扩展指令的空间。
The evolution of applications in fields like media processing and software definition radio (SDR) continuously brings more complex algorithms. The demand for high-quality services requires huge volumes of data processed under given time and resource constraints. Traditional VLIW and superscalar processors do not scale well because the area, delay, and power consumption of centralized register files increase proportionally to O(N2), O(N), and O(log4N) respectively as the number of access ports N increases. Meanwhile, the control paths of these processors, such as instruction issuing and commitment, are organized in a centralized manner, which results in high complexity and poor scalability.
Multiprocessor System-on-Chips (MPSoCs) have emerged in the past decade as promising solutions to meet the computation requirement. However, integrating multiple cores on a single chip does not directly increase processors’performance or power efficiency for most sequentially written applications. The dilemma stemming from parallelizing sequential programs or writing parallel programs to take full advantage of available resources in MPSoCs drives us to rethink about the uni-core solutions from a hardware/software codesign perspective: What are the fundamental limitations of uni-core processors? How to eliminate these limitations and reduce hardware complexity? How to speedup applications with minimal modification to the architecture of state-of-the art processors? The main contributions of this paper are summarized as follows:
1) We analyzed the inefficiency of a uni-core VLIW processor in processing two typical computation-intensive benchmarks from the area of media processing and software defined radio, and tried to find out fundamental limitations that hinder the scalability, performance and power efficiency of uni-core solutions. We drew the conclusion from the analysis that there are three aspects behind the inefficiency of uni-core processors, namely, the ultra-simplified instruction-set architecture (ISA) of RISC-like processors, the traditional plained binary instruction encoding scheme and centralized instruction execution control strategy. We proposed systmatical strategies to overcome the limitation of uni-core solutions based on the conclusion.
2) We proposed an automatic method that can fast enumerate candidate extended instructions. This method first profiles source codes and recognizes the ALU operations that account for most of the execution time, then, generate candidate extended instructions around these typical operations using windowed and progressive search processes. The result pattern from each search step is locally optimal, which guarantees the efficiency of the ultimate pattern to some extend. This instruction enumeration method can not only effectively explore the design space but also have linear complexity. The algorithm complexity grows linearly with the number of typical operatons and average search steps around each typical operation.
3) We proposed a novel resource compression method for extended instructions implemented on extended functional units. The method first finds out the critical path of an instruction and patitions the rest of the DFG (Date Flow Graph) of the instruction into multiple paths, then, finds out the MCES (Maximal Common Equivalent String) of all paths of all instructions and compresses these instructions contain the MCES. The method can guarantee resource be effectively shared among instructions. Meanwhile, the method allows modifying the DFG of an instruction through inserting simple operations into the paths of the instruction in order to reduce the number of inserted multiplexers and reduce the impact of multiplexers on area and delay.
4) We proposed a hardware/software instruction encoding scheme to improve the scalability of uni-core architectures. By statically scheduling a sequence of dependent instructions into a pack, implementing common information in the pack in a dedicated instruction word, and converting instruction issuing to pack issuing, we could substantially reduce the number of bits required to encode instructions and the hardware complexity of instruction issuing, thus improving the scalability usually limited by fixed-length instruction formats and centralized instruction issuing.
5) To improve the scalability and performance of uni-core processors, we proposed a novel distributed instruction execution control scheme and implement the pipeline using this scheme. The highly scalable pipeline that features in-order issuing, out-of-order execution and parallel but in-order commitment because the functional units partitioned among clusters are allowed to read operands, execute instructions, write back results and maintain data dependency themselves. The scalability is improved by the instruction execution control scheme, while the performance is enhanced by the increased hardware speed and the improved temporal data locality.
6) We proposed a novel ASIP architecture based on the scalable pipeline using distributed instruction execution control. The ASIP could support complex instructions which could have a maximum of 6 input operands and 2 output operands, which substantially extend the design space of extended instructions and improve the potential speedup from instruction customization. The execution resources like functional units and register file are patitioned among clusters, inter-cluter communication is implemented through a scalable operand passing network. Thus change in the functionality of extended fuctional units will not affect the baseline architecture.
过去10年里,片上多处理器(Multiprocessor System-on-Chip,MPSoC)证明是进一步提升处理器性能和功耗效率的有效方式之一。MPSoC通过将片上资源划分到多个处理器核中实现了多任务的并发运行,有利于减小处理器核的复杂度、降低MPSoC系统的工作频率、提高MPSoC系统的功耗效率。但串行编写的应用程序使得应用难以快速、高效地映射到MPSoC上。同时MPSoC的片上通信对处理器的性能、面积和功耗均产生一定的开销。这些因素使得MPSoC的性能并没有像预期的那样随集成电路技术带来的片上可用资源的增加而线性增加。
单处理器解决方案具有应用编程简单、资源通信开销小等优点。同时,基于传统处理器核对指令集、存储结构、通信协议等进行扩展构建面向应用的处理器证明是一种提升功耗效率的有效方式。因此,在MPSoC虽已成为处理器发展主流的时代有必要重新审视单处理器解决方案,找出限制单处理器的性能和功耗效率的关键因素,考虑单处理器满足数据计算密集型复杂应用的计算需求的可能。本文通过分析应用及其执行特征试图找出单处理器的根本缺陷,并在指令集定制、指令执行控制方式、可扩展指令编码、面向应用的处理器结构方面展开研究,提出了提升单处理器性能和功耗效率的相关技术。本文的研究内容和主要贡献如下:
1)分析了两种典型应用及其在VLIW结构处理器上的运行情况,总结了单处理器在处理计算密集型复杂应用方面的不足。通过分析发现,两种典型应用在任务级、循环级、基本块级和指令级多个层次均存在不同程度的并行性,且核心算法的计算模式相对固定。但是,传统处理器的指令执行控制方式和指令编码方式限制了处理器的可扩展性;传统的RISC处理器的指令集过于精简,不利于处理器的性能和功耗效率的提升;传统的充分考虑控制相关、数据相关和资源相关等信息的指令调度方式可扩展性差,不利于充分发挥处理器中可用资源的效能。
2)提出了一种快速的扩展指令集自动产生方法。该方法首先分析应用、获取应用中常用的算术逻辑操作,并以这些操作为中心采用加窗、步进等方式逐步增加扩展指令的复杂度,在保证每个步骤的输出均是局部最优结果的同时控制可算法复杂度。该方法不仅可以有效开发设计空间、产生高效的扩展指令,而且算法复杂度与典型操作的数量成正比,与以每个典型操作为中心进行的平均搜索步骤成正比,从而使得算法复杂度随应用复杂度的增加成线性增加。
3)提出了一种新的指令资源压缩方法。该方法首先找出扩展指令的关键路径并将指令的数据流图分割成多条件路径,然后将一条指令的路径与其它所有指令的路径一一匹对找出路径的最大公共等价子串,再以最大公共等价子串为索引压缩所有路径,从而保证了指令间的资源充分共享。同时,该方法允许对指令的数据流图进行修改,在路径中插入延迟和资源开销小的简单操作使路径或路径的一部分的数据流图与其它路径或者其它路径的一部分的数据流图等同,从而减小了插入的多路选择器的数量,减小了多路选择器产生的面积、延时开销。
4)提出了一种软/硬件协同的指令编码方法,旨在不显著增加代码尺寸的情况下消除指令编码对处理器的可扩展性的限制,同时保持原处理器的指令字长、指令集结构、硬件解码结构和编译调度算法不变。该方法基于簇型处理器(Clustered Processors)通过将派发到相同簇中的功能单元上执行的指令组合在一个指令包内,将包内指令的公共信息抽取出来以指令包头的形式插入包中,减小了指令字内需要编码的信息量,增加了固定长指令字的编码空间。同时,该方法对公共信息的类型以及包头指令的数量没有限制,从而提高了该方法的可扩展性。
5)提出了一种集中式和分布式相结合的指令执行控制机制,即取指、译码和流出仍采用集中控制方式,指令的执行和写回采用分布式控制方式。这种机制将指令的译码和流出由原来的指令级转变成指令包级,简化了指令流出的复杂度。同时,该机制将指令执行过程中的取数、执行、写回三个环节的控制过程交给功能单元和分布式寄存器文件,不仅简化了控制逻辑的复杂度而且实现了控制机制的可扩展性。此外,该机制允许产生数据的指令输出一旦有效后马上就能被消费数据的指令使用,提高了处理器开发数据局部性的能力。
6 )基于一种可扩展的簇型处理器提出了可以支持复杂指令的ASIP(Application-Specific Instruction-set Processor)结构。该ASIP的基本结构中的功能单元、寄存器文件被划分到多个簇中,各个簇可以自行管理派发到簇内的指令的执行并通过可扩展的操作数传递网实现簇间通信。因而,向基本结构中添加包含扩展功能单元的扩展簇时不影响其它的结构和资源分配,从而减小了ASIP的设计复杂度。同时,扩展功能单元允许扩展指令具有最多6个输入操作数和最多2个输出操作数,允许扩展指令具有更高的复杂度,极大地拓展了扩展指令的空间。
The evolution of applications in fields like media processing and software definition radio (SDR) continuously brings more complex algorithms. The demand for high-quality services requires huge volumes of data processed under given time and resource constraints. Traditional VLIW and superscalar processors do not scale well because the area, delay, and power consumption of centralized register files increase proportionally to O(N2), O(N), and O(log4N) respectively as the number of access ports N increases. Meanwhile, the control paths of these processors, such as instruction issuing and commitment, are organized in a centralized manner, which results in high complexity and poor scalability.
Multiprocessor System-on-Chips (MPSoCs) have emerged in the past decade as promising solutions to meet the computation requirement. However, integrating multiple cores on a single chip does not directly increase processors’performance or power efficiency for most sequentially written applications. The dilemma stemming from parallelizing sequential programs or writing parallel programs to take full advantage of available resources in MPSoCs drives us to rethink about the uni-core solutions from a hardware/software codesign perspective: What are the fundamental limitations of uni-core processors? How to eliminate these limitations and reduce hardware complexity? How to speedup applications with minimal modification to the architecture of state-of-the art processors? The main contributions of this paper are summarized as follows:
1) We analyzed the inefficiency of a uni-core VLIW processor in processing two typical computation-intensive benchmarks from the area of media processing and software defined radio, and tried to find out fundamental limitations that hinder the scalability, performance and power efficiency of uni-core solutions. We drew the conclusion from the analysis that there are three aspects behind the inefficiency of uni-core processors, namely, the ultra-simplified instruction-set architecture (ISA) of RISC-like processors, the traditional plained binary instruction encoding scheme and centralized instruction execution control strategy. We proposed systmatical strategies to overcome the limitation of uni-core solutions based on the conclusion.
2) We proposed an automatic method that can fast enumerate candidate extended instructions. This method first profiles source codes and recognizes the ALU operations that account for most of the execution time, then, generate candidate extended instructions around these typical operations using windowed and progressive search processes. The result pattern from each search step is locally optimal, which guarantees the efficiency of the ultimate pattern to some extend. This instruction enumeration method can not only effectively explore the design space but also have linear complexity. The algorithm complexity grows linearly with the number of typical operatons and average search steps around each typical operation.
3) We proposed a novel resource compression method for extended instructions implemented on extended functional units. The method first finds out the critical path of an instruction and patitions the rest of the DFG (Date Flow Graph) of the instruction into multiple paths, then, finds out the MCES (Maximal Common Equivalent String) of all paths of all instructions and compresses these instructions contain the MCES. The method can guarantee resource be effectively shared among instructions. Meanwhile, the method allows modifying the DFG of an instruction through inserting simple operations into the paths of the instruction in order to reduce the number of inserted multiplexers and reduce the impact of multiplexers on area and delay.
4) We proposed a hardware/software instruction encoding scheme to improve the scalability of uni-core architectures. By statically scheduling a sequence of dependent instructions into a pack, implementing common information in the pack in a dedicated instruction word, and converting instruction issuing to pack issuing, we could substantially reduce the number of bits required to encode instructions and the hardware complexity of instruction issuing, thus improving the scalability usually limited by fixed-length instruction formats and centralized instruction issuing.
5) To improve the scalability and performance of uni-core processors, we proposed a novel distributed instruction execution control scheme and implement the pipeline using this scheme. The highly scalable pipeline that features in-order issuing, out-of-order execution and parallel but in-order commitment because the functional units partitioned among clusters are allowed to read operands, execute instructions, write back results and maintain data dependency themselves. The scalability is improved by the instruction execution control scheme, while the performance is enhanced by the increased hardware speed and the improved temporal data locality.
6) We proposed a novel ASIP architecture based on the scalable pipeline using distributed instruction execution control. The ASIP could support complex instructions which could have a maximum of 6 input operands and 2 output operands, which substantially extend the design space of extended instructions and improve the potential speedup from instruction customization. The execution resources like functional units and register file are patitioned among clusters, inter-cluter communication is implemented through a scalable operand passing network. Thus change in the functionality of extended fuctional units will not affect the baseline architecture.
引文
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