一种极低功耗模拟IC设计技术及其在高性能音频模数转换器中的应用研究
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摘要
为了满足便携式电子产品的迫切需求以及大型电子系统的节能需要,低压低功耗设计已经成为未来CMOS集成电路发展的主流方向。采用基于C类反相器的设计来代替传统的运算放大器是解决极低功耗低压IC设计难题的一种有效手段,其中反相器输入MOS管在大多数时间内都工作在亚阈值区,大大降低了电源电压和系统功耗。但是,传统C类反相器增益偏低,不适合许多高精度应用场合,例如级联结构ΣA模数转换器(ADC),而且由于其亚阈值工作特征及推挽电路结构,性能指标受工艺偏差和电源电压变化的影响非常严重,容易造成其应用电路性能下降甚至功能丧失,使其不具备工业实用性。本论文针对基于C类反相器的极低功耗IC设计技术进行了较为深入系统的研究,通过电路创新对传统C类反相器进行改造,推出了新一代C类反相器概念。为证明该新一代C类反相器的实用性,本论文将其应用到级联结构音频ΣΔADC的设计实现中,在功耗与性能方面均获得了令人满意的效果。论文主要工作和创新点包括：
1、针对传统C类反相器直流增益偏低的问题,提出了增益自举型C类反相器概念并对其进行了深入的理论研究及设计实现。通过理论计算和软件仿真详细分析了增益自举型C类反相器的各项指标,包括直流增益、带宽、功耗、输出摆幅、输入失调、电源抑制比、共模抑制比、噪声、摆率和建立时间等；提出了“类转换”、最大摆率和有效摆率概念、以及计算摆率时“三角形近似”和“多边形近似”算法等。与传统C类反相器相比,增益自举型C类反相器可使直流增益从51.7dB显著提高到75.2dB。
2、针对传统C类反相器受制造工艺、电源电压和温度(PVT)影响严重的问题,提出了一种面向成品率增强的片上体偏置技术,用于补偿PVT变化对模拟／数模混合IC(尤其是低功耗亚阈值IC)性能的不利影响。同时,提出了三种体偏置实现电路(简单型、移位型和计数型),并从体电位调节范围、精度、速度、面积和功耗等指标入手,对三种体偏置实现电路的各项指标进行了详细的理论分析与计算。对其中部分实现电路进行了版图设计和流片。
3、基于增益自举技术加片上体偏置技术的新一代C类反相器技术的应用研究。音频∑△ADC是数模混合IC的典型代表,其模拟电路部分主要是一个ΣA调制器。本论文选择∑△ADC及其∑△调制器作为应用研究的目标,实现了基于上述新一代C类反相器技术的高性能低功耗音频ΣΔ ADC,以及极低功耗低压ΣA调制器。
4、流片及测试。基于上述新一代C类反相器技术的音频ΣΔADC芯片在65nm标准CMOS工艺和1.2V电源电压下能够达到97dB的动态范围、95dB的信噪比和92dB的信噪失真比,功耗为1.13mW。与同批次未使用该技术的对比芯片相比,测试所得综合性能指标)从1.87pJ／量化电平优化到0.93pJ/量化电平。另外,为追求更优的综合指标,本论文实现了极低功耗低压EΔ调制器芯片,该调制器芯片在0.8V电源电压下和音频带宽内能够达到98dB的动态范围、93dB的信噪比和90dB的信噪失真比,功耗为230μW,测试所得FOM指标与国际上高水平期刊最近几年发表的论文水平相当,达到了国际先进水平。
To copy with the urgent demand of portable electronic products as well as the need of saving energy in large electronic systems, low-voltage low-power design has become the mainstream of future CMOS IC development. A class-C inverter is recently reported to replace traditional OTA to meet the low-power low-voltage IC design challenges. The input transistors of the inverter operate in a sub-threshold region most of the time, thereby minimizing the supply voltage and power dissipation. However, the DC-gain of a traditional class-C inverter is finite, which is not suitable for many high-precision applications, such as cascade ΣΔ ADC. Moreover, because of its push-pull structure and sub-threshold characteristics, the inverter is strongly sensitive to process and supply voltage variation, which is likely to cause performance degradation or even malfunction of its application circuits. This thesis carries out thorough and systematic research focusing on the inverter-based ultra-low-power IC design technique, optimizes traditional class-C inverter through circuit innovation, and proposes a new generation of class-C inverter. In order to prove the practicality of the new generation of class-C inverter, the thesis implements an inverter-based cascade audio ΣΔ ADC, whose specifications of power consumption and performance are satisfactory. The main work and innovations include:
1. In view of the problem that the DC-gain of traditional class-C inverter is low, the thesis proposes the concept, in-depth theoretical study and design implementation of a gain-boost class-C inverter. Various specifications of the gain-boost inverter are analyzed in detail by theoretical calculation and software simulation, including DC-gain, bandwidth, power consumption, output swing, input offset, PSRR, CMRR, noise, SR and settling time; Concepts of "approximate slew", maximum SR and effective SR are proposed;"triangular approximation" and "polygonal approximation" algorithms for SR calculation are povided. Compared with traditional class C inverter, the gain-boost inverter significantly increases the DC-gain from51.7dB to75.2dB.
2. In view of the problem that traditional class-C inverter is sensitive to PVT-variations, an on-chip body bias technique for the enhancement of parametric yield is proposed, which is used to compensate for PVT-variations in analog/mixed-signal IC, especially in low-voltage low-power sub-threshold IC. Meanwhile, three body bias implementation circuits (simple type, shift type and count type) are proposed. A detailed theoretical analysis and calculation is carried out for the specifications of the three body bias circuit, including body potential adjustment range, accuracy, speed, area and power consumption. A part of the body bias circuits are layout designed and tapeout.
3. Application research of a new generation of class-C inverter which is based on gain-boost technique and on-chip body bias technique. Audio EA ADC is a typical representative of mixed-signaled IC, whose analog part is mainly a EA modulator. The thesis chooses ΣΔ ADC and its inside ΣΔ modulator as application circuits, and implements a high-performance, low-power audio ΣΔ ADC as well as an ultra low-power low-voltage ΣΔ modulator based on the new generation of class-C inverter.
4. Tapeout and test. The proposed inverter-based audio ΣΔ ADC chip is implemented in65nm stardard CMOS process, and achieve97-dB DR,95-dB SNR and92-dB SNDR at1.2-V supply consuming1.13mW. Compared with the OTA-based chip (without the class-C inverter) of the same batch, the measured of the inverter-based chip is optimizated from1.87pJ/step to0.93pJ/step. In addition, for the pursuit of better FOM specification, the thesis implements an ultra-low-power low-voltage EA modulator chip. The modulator chip can achieve98-dB DR,93-dB SNR and90-dB SNDR over20-KHz bandwidth at0.8-V supply consuming230μW. The measured FOM specification is comparable with the international high-level journal papers published in recent years, reaching international advanced level.
1、针对传统C类反相器直流增益偏低的问题,提出了增益自举型C类反相器概念并对其进行了深入的理论研究及设计实现。通过理论计算和软件仿真详细分析了增益自举型C类反相器的各项指标,包括直流增益、带宽、功耗、输出摆幅、输入失调、电源抑制比、共模抑制比、噪声、摆率和建立时间等；提出了“类转换”、最大摆率和有效摆率概念、以及计算摆率时“三角形近似”和“多边形近似”算法等。与传统C类反相器相比,增益自举型C类反相器可使直流增益从51.7dB显著提高到75.2dB。
2、针对传统C类反相器受制造工艺、电源电压和温度(PVT)影响严重的问题,提出了一种面向成品率增强的片上体偏置技术,用于补偿PVT变化对模拟／数模混合IC(尤其是低功耗亚阈值IC)性能的不利影响。同时,提出了三种体偏置实现电路(简单型、移位型和计数型),并从体电位调节范围、精度、速度、面积和功耗等指标入手,对三种体偏置实现电路的各项指标进行了详细的理论分析与计算。对其中部分实现电路进行了版图设计和流片。
3、基于增益自举技术加片上体偏置技术的新一代C类反相器技术的应用研究。音频∑△ADC是数模混合IC的典型代表,其模拟电路部分主要是一个ΣA调制器。本论文选择∑△ADC及其∑△调制器作为应用研究的目标,实现了基于上述新一代C类反相器技术的高性能低功耗音频ΣΔ ADC,以及极低功耗低压ΣA调制器。
4、流片及测试。基于上述新一代C类反相器技术的音频ΣΔADC芯片在65nm标准CMOS工艺和1.2V电源电压下能够达到97dB的动态范围、95dB的信噪比和92dB的信噪失真比,功耗为1.13mW。与同批次未使用该技术的对比芯片相比,测试所得综合性能指标)从1.87pJ／量化电平优化到0.93pJ/量化电平。另外,为追求更优的综合指标,本论文实现了极低功耗低压EΔ调制器芯片,该调制器芯片在0.8V电源电压下和音频带宽内能够达到98dB的动态范围、93dB的信噪比和90dB的信噪失真比,功耗为230μW,测试所得FOM指标与国际上高水平期刊最近几年发表的论文水平相当,达到了国际先进水平。
To copy with the urgent demand of portable electronic products as well as the need of saving energy in large electronic systems, low-voltage low-power design has become the mainstream of future CMOS IC development. A class-C inverter is recently reported to replace traditional OTA to meet the low-power low-voltage IC design challenges. The input transistors of the inverter operate in a sub-threshold region most of the time, thereby minimizing the supply voltage and power dissipation. However, the DC-gain of a traditional class-C inverter is finite, which is not suitable for many high-precision applications, such as cascade ΣΔ ADC. Moreover, because of its push-pull structure and sub-threshold characteristics, the inverter is strongly sensitive to process and supply voltage variation, which is likely to cause performance degradation or even malfunction of its application circuits. This thesis carries out thorough and systematic research focusing on the inverter-based ultra-low-power IC design technique, optimizes traditional class-C inverter through circuit innovation, and proposes a new generation of class-C inverter. In order to prove the practicality of the new generation of class-C inverter, the thesis implements an inverter-based cascade audio ΣΔ ADC, whose specifications of power consumption and performance are satisfactory. The main work and innovations include:
1. In view of the problem that the DC-gain of traditional class-C inverter is low, the thesis proposes the concept, in-depth theoretical study and design implementation of a gain-boost class-C inverter. Various specifications of the gain-boost inverter are analyzed in detail by theoretical calculation and software simulation, including DC-gain, bandwidth, power consumption, output swing, input offset, PSRR, CMRR, noise, SR and settling time; Concepts of "approximate slew", maximum SR and effective SR are proposed;"triangular approximation" and "polygonal approximation" algorithms for SR calculation are povided. Compared with traditional class C inverter, the gain-boost inverter significantly increases the DC-gain from51.7dB to75.2dB.
2. In view of the problem that traditional class-C inverter is sensitive to PVT-variations, an on-chip body bias technique for the enhancement of parametric yield is proposed, which is used to compensate for PVT-variations in analog/mixed-signal IC, especially in low-voltage low-power sub-threshold IC. Meanwhile, three body bias implementation circuits (simple type, shift type and count type) are proposed. A detailed theoretical analysis and calculation is carried out for the specifications of the three body bias circuit, including body potential adjustment range, accuracy, speed, area and power consumption. A part of the body bias circuits are layout designed and tapeout.
3. Application research of a new generation of class-C inverter which is based on gain-boost technique and on-chip body bias technique. Audio EA ADC is a typical representative of mixed-signaled IC, whose analog part is mainly a EA modulator. The thesis chooses ΣΔ ADC and its inside ΣΔ modulator as application circuits, and implements a high-performance, low-power audio ΣΔ ADC as well as an ultra low-power low-voltage ΣΔ modulator based on the new generation of class-C inverter.
4. Tapeout and test. The proposed inverter-based audio ΣΔ ADC chip is implemented in65nm stardard CMOS process, and achieve97-dB DR,95-dB SNR and92-dB SNDR at1.2-V supply consuming1.13mW. Compared with the OTA-based chip (without the class-C inverter) of the same batch, the measured of the inverter-based chip is optimizated from1.87pJ/step to0.93pJ/step. In addition, for the pursuit of better FOM specification, the thesis implements an ultra-low-power low-voltage EA modulator chip. The modulator chip can achieve98-dB DR,93-dB SNR and90-dB SNDR over20-KHz bandwidth at0.8-V supply consuming230μW. The measured FOM specification is comparable with the international high-level journal papers published in recent years, reaching international advanced level.
引文
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