CMMB移动数字电视调谐器中频率综合器的研究与设计
摘要
本文论述了应用于中国移动多媒体广播(CMMB)标准下的射频调谐器中的频率综合器的设计与实现,在对标准进行深入分析和理解之后,对整个系统进行合理定义,并给出对于频率综合器的合适的系统要求指标,然后基于这个指标要求进行后续的建模设计。
在对调谐器系统进行分析的时候,着重分析了使用零中频接收机结构的优点和需要注意的关键问题,以及调谐器系统相对于其他的收发机系统所考虑的不同的问题。对于指标的确定是来自于对CMMB标准的合理推导,既符合标准要求,同时又避免了过度设计的问题。
在设计频率综合器时,首先采用线性化的模型对频率综合器系统进行模块参数的确定和优化,一方面给模块设计提供依据,另一方面能够从系统上合理把握不同模块之间的权衡,达到最佳的设计效果。
电路级的设计涵盖了射频,模拟,数字电路的设计,对于射频电路的设计,主要是指VCO的设计,难点在于制作合适的电感,提高其品质因数,同时合理的选择VCO的结构也是非常重要的,不断的优化相位噪声是VCO设计中最关键的内容；对于模拟电路的设计,主要是指电荷泵的设计,设计目标是尽量的提高电荷泵的线性化程度,并且在条件允许的情况下,尽量提高其电源抑制能力；对于数字电路的设计,主要是指高频的分频器的设计(最大工作频率超过1GHz),这里的重点在于异步数字电路定制过程中的时序问题,以及尽量用最小的功耗达到最高的分频频率,总之,整个频率综合器的设计是对于射频,模拟,数字电路设计的一个总结和综合能力的体现。
最后,本文论述的频率综合器在UMC0.18um工艺下进行了一次流片,并一次流片成功,测试结果与仿真结果非常接近,所有性能指标均达到设计初期设定的性能指标,说明整个频率综合器设计的流程的正确性和优化电路的必要性。
The design and implementation of a frequency synthesizer used in the CMMB standard mobile TV tuner is presented in this thesis. After down to the earth analysis of the standard, the system level specification is defined. All the block level circuit designs are based on this specification. System level modeling of frequency synthesizer is essential for the circuit level design for this PLL afterwards.
The main attention is paid on analyzing the advantages and fundamental issues in the zero-IF receiver architecture during the TV tuner system level definition. The different problems faced by the TV tuner application are also considered. The specifications are made during the careful thought on the CMMB standard. Over-design issue is eliminated; meanwhile, standard specification is well followed.
During the design of the whole frequency synthesizer, the linear model is used both in the block level specification definition and the phase noise optimization procedure. This model is very important, it provides the performance requirements for the circuit blocks, at the same time, shows the trade-offs among different building blocks for the performance optimization.
The circuit level design of the synthesizer is the combination of the RF, analog and digital circuit design capability. VCO design is the main part of the RF circuit. The difficult issue is how to make a high Q inductor with reasonable area consumption. Choosing a better VCO structure is another thing to be considered. The most important performance requirement for the VCO is the phase noise. For the analog part, designing a more linear charge pump with large PSRR is the key issue. For the digital part, a high speed (more than 1 GHz) fully customized frequency divider is designed with low power and higher stable working frequency. For all, the design of a high performance frequency synthesizer shows ones'capability in RF, analog and digital circuits.
The synthesizer designed in this thesis is fabricated in UMC 0.18um CMOS technology with first-pass. The measurement results meet the simulation very well. All the performance beat the specification defined in the early phase of the whole design period. The design procedure and the optimization for the circuit are verified during the whole process.
在对调谐器系统进行分析的时候,着重分析了使用零中频接收机结构的优点和需要注意的关键问题,以及调谐器系统相对于其他的收发机系统所考虑的不同的问题。对于指标的确定是来自于对CMMB标准的合理推导,既符合标准要求,同时又避免了过度设计的问题。
在设计频率综合器时,首先采用线性化的模型对频率综合器系统进行模块参数的确定和优化,一方面给模块设计提供依据,另一方面能够从系统上合理把握不同模块之间的权衡,达到最佳的设计效果。
电路级的设计涵盖了射频,模拟,数字电路的设计,对于射频电路的设计,主要是指VCO的设计,难点在于制作合适的电感,提高其品质因数,同时合理的选择VCO的结构也是非常重要的,不断的优化相位噪声是VCO设计中最关键的内容；对于模拟电路的设计,主要是指电荷泵的设计,设计目标是尽量的提高电荷泵的线性化程度,并且在条件允许的情况下,尽量提高其电源抑制能力；对于数字电路的设计,主要是指高频的分频器的设计(最大工作频率超过1GHz),这里的重点在于异步数字电路定制过程中的时序问题,以及尽量用最小的功耗达到最高的分频频率,总之,整个频率综合器的设计是对于射频,模拟,数字电路设计的一个总结和综合能力的体现。
最后,本文论述的频率综合器在UMC0.18um工艺下进行了一次流片,并一次流片成功,测试结果与仿真结果非常接近,所有性能指标均达到设计初期设定的性能指标,说明整个频率综合器设计的流程的正确性和优化电路的必要性。
The design and implementation of a frequency synthesizer used in the CMMB standard mobile TV tuner is presented in this thesis. After down to the earth analysis of the standard, the system level specification is defined. All the block level circuit designs are based on this specification. System level modeling of frequency synthesizer is essential for the circuit level design for this PLL afterwards.
The main attention is paid on analyzing the advantages and fundamental issues in the zero-IF receiver architecture during the TV tuner system level definition. The different problems faced by the TV tuner application are also considered. The specifications are made during the careful thought on the CMMB standard. Over-design issue is eliminated; meanwhile, standard specification is well followed.
During the design of the whole frequency synthesizer, the linear model is used both in the block level specification definition and the phase noise optimization procedure. This model is very important, it provides the performance requirements for the circuit blocks, at the same time, shows the trade-offs among different building blocks for the performance optimization.
The circuit level design of the synthesizer is the combination of the RF, analog and digital circuit design capability. VCO design is the main part of the RF circuit. The difficult issue is how to make a high Q inductor with reasonable area consumption. Choosing a better VCO structure is another thing to be considered. The most important performance requirement for the VCO is the phase noise. For the analog part, designing a more linear charge pump with large PSRR is the key issue. For the digital part, a high speed (more than 1 GHz) fully customized frequency divider is designed with low power and higher stable working frequency. For all, the design of a high performance frequency synthesizer shows ones'capability in RF, analog and digital circuits.
The synthesizer designed in this thesis is fabricated in UMC 0.18um CMOS technology with first-pass. The measurement results meet the simulation very well. All the performance beat the specification defined in the early phase of the whole design period. The design procedure and the optimization for the circuit are verified during the whole process.
引文
[1]Iason Vassiliou, Nikos Haralabidis, and Kostis Vavelidis, "Multimedia Broadcasting Standards:Technology and Practice", Springer Science and Business Media, LLC 2009.
[2]国家广播电影电视总局,移动多媒体广播第七部分：接收解码终端技术要求(GY/T 220.7-2008).
[3]Analog Devices, ADMTV102, Tuner IC for DVB-H, DVB-T, and DMB-TH, 2007.
[4]Tom A. D. Riley, Miles A. Copeland, Tad A. Kwasniewski, "Delta-Sigma Modulation in Fractional-N Frequency Synthesis", IEEE J. Solid-State Circuits, vol.28, No.5, May 1993.
[5]Thomas H. Lee, "The Design of CMOS Radio-Frequency Integrated Circuits Second Edition", Cambridge University Press,2004.
[6]Keliu Shu, Edgar Sanchez-Sinencio, "CMOS PLL Synthesizers:Analysis and Design", Springer,2005.
[7]A. Hajimiri and T. H. Lee, "A General Theory of Phase Noise in Electrical Oscillators," IEEE J. Solid-State Circuits, vol.33, Feb.1998
[8]W. Rhee, "Multi-bit Delta-Sigma Modulation Technique for Fractional-N Frequency Synthesizers", PhD Dissertation, M.S., University of California at Los Angeles,1993.
[9]Kun-Seok Lee, Hwayeal Yu, Hyung Ki Ahn, Hyoung-Seok Oh, Seonghan Ryu, Dongjin Keum, Byeong-Ha Park, "A 0.13-um CMOS Sigma-Delta Frequency Synthesizer with An Area Optimizing Low-pass Filter, Fast AFC time, and A Wideband VCO for WCDMA/GSM/GPRS/EDGE Applications", Radio Frequency Integrated Circuits Symposium,2008.
[10]Lei Lu, Zhichao Gong, Youchun Liao, Hao Min, Zhangwen Tang, "A 975-to-1960Mhz Fast-Locking Fractional-N Synthesizer with Adaptive Bandwidth Control and 4/4.5 Prescaler for Digital TV Tuners", Solid-State Circuits Conference-Digest of Technical Papers,2009.
[11]Lin, T.-H., Lai, Y.-J., "An Agile VCO Frequency Calibration Technique for A 10-GHz CMOS PLL", IEEE J. Solid-State Circuits, Vol.42, Oct.2007.
[12]Marutani, M., Anbutsu, H., Kondo, M., Shirai, N., Yamazaki, H., Watanabe, Y, "An 18mW 90 to 770MHz Synthesizer with Agile Auto-tuning for Digital TV-Tuners", Solid-State Circuits Conference,2006.
[2]国家广播电影电视总局,移动多媒体广播第七部分：接收解码终端技术要求(GY/T 220.7-2008).
[3]Analog Devices, ADMTV102, Tuner IC for DVB-H, DVB-T, and DMB-TH, 2007.
[4]Tom A. D. Riley, Miles A. Copeland, Tad A. Kwasniewski, "Delta-Sigma Modulation in Fractional-N Frequency Synthesis", IEEE J. Solid-State Circuits, vol.28, No.5, May 1993.
[5]Thomas H. Lee, "The Design of CMOS Radio-Frequency Integrated Circuits Second Edition", Cambridge University Press,2004.
[6]Keliu Shu, Edgar Sanchez-Sinencio, "CMOS PLL Synthesizers:Analysis and Design", Springer,2005.
[7]A. Hajimiri and T. H. Lee, "A General Theory of Phase Noise in Electrical Oscillators," IEEE J. Solid-State Circuits, vol.33, Feb.1998
[8]W. Rhee, "Multi-bit Delta-Sigma Modulation Technique for Fractional-N Frequency Synthesizers", PhD Dissertation, M.S., University of California at Los Angeles,1993.
[9]Kun-Seok Lee, Hwayeal Yu, Hyung Ki Ahn, Hyoung-Seok Oh, Seonghan Ryu, Dongjin Keum, Byeong-Ha Park, "A 0.13-um CMOS Sigma-Delta Frequency Synthesizer with An Area Optimizing Low-pass Filter, Fast AFC time, and A Wideband VCO for WCDMA/GSM/GPRS/EDGE Applications", Radio Frequency Integrated Circuits Symposium,2008.
[10]Lei Lu, Zhichao Gong, Youchun Liao, Hao Min, Zhangwen Tang, "A 975-to-1960Mhz Fast-Locking Fractional-N Synthesizer with Adaptive Bandwidth Control and 4/4.5 Prescaler for Digital TV Tuners", Solid-State Circuits Conference-Digest of Technical Papers,2009.
[11]Lin, T.-H., Lai, Y.-J., "An Agile VCO Frequency Calibration Technique for A 10-GHz CMOS PLL", IEEE J. Solid-State Circuits, Vol.42, Oct.2007.
[12]Marutani, M., Anbutsu, H., Kondo, M., Shirai, N., Yamazaki, H., Watanabe, Y, "An 18mW 90 to 770MHz Synthesizer with Agile Auto-tuning for Digital TV-Tuners", Solid-State Circuits Conference,2006.
© 2004-2018 中国地质图书馆版权所有 京ICP备05064691号 京公网安备11010802017129号 地址：北京市海淀区学院路29号 邮编：100083 电话：办公室：(+86 10)66554848；文献借阅、咨询服务、科技查新：66554700 |