P-41: A Low-Power ESL a-IZGO TFT Integrated Gate Driver Circuit

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• 作者：Shijie Cao ; Zhijin Hu ; Congwei Liao ; Cuicui Wang ; Jia Fan ; Min Zhang and Shengdong Zhang
• 刊名：SID Symposium Digest of Technical Papers
• 出版年：2016
• 出版时间：May 2016
• 年：2016
• 卷：47
• 期：1
• 页码：1272-1275
• 全文大小：1819K
• ISSN：2168-0159

文摘

A low-power ESL a-IGZO TFT integrated gate driver, where the gate level of driving-transistor is kept lower than the source/drain level to suppress the serious clock-feed-through effect induced by the large parasitic capacitance of the ESL structured driving TFT. Moreover, a new inverter is designed to minimize internal leakage current. Thus, the dependence of power consumption in the gate driver on the overlap-length between gate and source/drain of driving TFT and the bootstrapping capacitor is much lessened. Simulation results verify the feasibility of the proposed gate driver with 16 stages and manifest that the power consumption is smaller than half of the conventional one with the same simulation parameters.