Due to the achieved results the stability-power dissipation ratio (SPR), the evaluation parameter in SRAM memories, is improved about 7 for 8T-SRAM which is implemented with a stack forcing method in similar carbon nanotube field-effect transistor (CNTFET) technology.
Finally the 4×4 SRAM memory is proposed based on 1×1 SRAM with the help of 8T-SRAM. This memory is presented with array structures for reading and writing blocks.
The simulation results reveal that the Power-Delay Product (PDP) term decreases 18% and 36% in the reading and writing cycles respectively for the stack forcing SRAM with the same array.
The simulation is done with H-SPICE software in 32 nm technology under the condition of 0.9 V supply voltage, 500 MHz frequency and room temperature.