Low voltage high performance hybrid full adder

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• 作者：Pankaj Kumar ; ^{pankajkumar_6120011@nitkkr.ac.in" class="auth_mail" title="E-mail the corresponding author} ; Rajender Kumar Sharma
• 关键词：High speed ; Low voltage ; Logic structure ; Hybrid adder
• 刊名：Engineering Science and Technology,an International Journal
• 出版年：2016
• 出版时间：March 2016
• 年：2016
• 卷：19
• 期：1
• 页码：559-565
• 全文大小：2117 K

文摘

This paper presents a low voltage and high performance 1-bit full adder designed with an efficient internal logic structure that leads to have a reduced Power Delay Product (PDP). The modified NOR and NAND gates, an essential entity, are also presented. The circuit is designed with cadence virtuoso tool with UMC 90-nm and 55-nm CMOS technologies. The proposed adder is compared with some of the popular adders based on power consumption, speed and power delay product. The proposed full adder cells achieve 56% and 76.69% improvement in speed and power delay product metric when compared with conventional C-CMOS full adder. It is also found that the proposed adder cells exhibit excellent signal integrity and driving capability when operated at low voltages.