Single event double node upset tolerance in MOS/spintronic sequential and combinational logic circuits

详细信息    查看全文

• 作者：Ramin Rajaei ^{r_rajaei@sbu.ac.ir}
• 关键词：STT-MRAM ; Magnetic tunnel junction (MTJ) ; Nonvolatility ; Radiation immunity ; Soft error ; Single event upset (SEU) ; Single event double node upset (SEDU)
• 刊名：Microelectronics Reliability
• 出版年：2017
• 出版时间：February 2017
• 年：2017
• 卷：69
• 期：Complete
• 页码：109-114
• 全文大小：885 K
• 卷排序：69

文摘

Spin-transfer torque random access memory (STT-RAM) is an emerging storage technology that is considered widely thanks to its attractive features such as low power consumption, nonvolatility, scalability and high density. STT-RAMs are comprised of a hybrid design of CMOS and spintronic units. Magnetic tunnel junction (MTJ) as the basic element of such hybrid technology is inherently robust against radiation induced faults. However, the peripheral CMOS component for sensing the resistance of the MTJs are prone to be affected by energetic particles. This paper proposes low power, nonvolatile and radiation hardened latch and lookup table circuits based on hybrid CMOS/MTJ technology for the next generation integrated circuit devices. Simulation results revealed that, the proposed circuits are fully robust against single event upsets (SEU) and also single event double node upsets (SEDU) that are of the main reliability challenging issues in current sub-nanometer CMOS technologies.