Low-power low-noise analog signal conditioning chip with on-chip drivers for healthcare applications

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• 作者：Sanjay Joshi ; Viral Thaker ; Anvesha Amaravati ; Maryam Shojaei-Baghini
• 关键词：Chopper modulated instrumentation amplifier ; Driven right leg circuit ; Shield drive amplifier ; Spike removal filter
• 刊名：Microelectronics Journal
• 出版年：2012
• 出版时间：November, 2012
• 年：2012
• 卷：43
• 期：11
• 页码：828-837
• 全文大小：2101 K

文摘

This paper presents an ultra low-noise, low-voltage complete analog signal conditioning chip, fabricated in 180 nm mixed-mode CMOS process. In contrast to many already-reported biomedical chips the test chip has been fabricated in a relatively scaled technology operating at low supply voltage of 1.8 V. This enables targeting energy-efficient hand-held biomedical devices where low-noise analog signal conditioning, preliminary processing and low-power wireless functionalities will be integrated on one chip. The test chip features instrumentation amplifier (INA) with chopper modulation at the first stage. The second stage is a novel area efficient spike removal filter (SRF) for attenuating coupled chopping spikes. The last stage is a differential active RC filter to adjust gain and bandwidth of the forward channel. On-chip non-overlapping clock generators with frequency of 4 kHz and 8 kHz for SRF stage are also implemented on the test. The chip also features a reconfigurable driven-right-leg circuit (DRLC) and shield drive amplifier (SDA) in the feedback path specifically for portable healthcare instruments. The DRLC provides the feedback either with operational amplifier (op-amp) or operational transconductance amplifier (OTA), configurable by the user. The presented test chip, for the first time, demonstrates an integrated OTA-based DRLC along with INA. INA and drivers have been designed and optimized for minimum power dissipation using a power-oriented design flow. The measurement results show that the INA achieves input-referred noise density of and DC current of maintaining minimum of 109 dB at 1.91 kHz. Measurements also show that 34 dB interference reduction at 50 Hz is achieved with DRLC. Low operating voltage, wide range of specifications and reconfigurable modules and interconnections enable the chip to be used for broad range of signal conditioning applications.