FPGA acceleration using high-level languages of a Monte-Carlo method for pricing complex options

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• 作者：Diego Sanchez-Roman ^{d.sanchez@uam.es}Author Vitae ; Victor Moreno ; ^{victor.moreno@uam.es}Author Vitae ; Sergio Lopez-Buedo ^{sergio.lopez-buedo@uam.es}Author Vitae ; Gustavo Sutter ^{gustavo.sutter@uam.es}Author Vitae ; Ivan Gonzalez ^{ivan.gonzalez@uam.es}Author Vitae ; Francisco J. Gomez-Arribas ^{francisco.gomez@uam.es}Author Vitae ; Javier Aracil ^{javier.aracil@uam.es}Author Vitae
• 关键词：High level language synthesis ; Field programmable gate arrays ; Financial data processing ; Parallel machines ; Floating-point arithmetic
• 刊名：Journal of Systems Architecture
• 出版年：2013
• 出版时间：March, 2013
• 年：2013
• 卷：59
• 期：3
• 页码：135-143
• 全文大小：411 K

文摘

In this paper we present an FPGA implementation of a Monte-Carlo method for pricing Asian options using Impulse C and floating-point arithmetic. In an Altera Stratix-V FPGA, a 149x speedup factor was obtained against an OpenMP-based solution in a 4-core Intel Core i7 processor. This speedup is comparable to that reported in the literature using a classic HDL-based methodology, but the development time is significantly reduced. Additionally, the use of a HLL-based methodology allowed us to implement a high-quality Gaussian random number generator, which produces more precise results than those obtained with the simple generators usually present in HDL-based designs.