Embedding the optimal all-to-all personalized exchange (ATAPE) on MINs⁺${}^{+}$ is proposed for the fast on-chip process.

Static ATAPE (D=S$D=S$ XOR $(C+\mathrm{order})$ mod N$N$) and f-in-1 dynamic ATAPE $(D=\rho \left[(S+C+\mathrm{order})\mathrm{mod}N\right])$ are ultimately embedded for full (S,D$S,D$)-routing on MINs⁺${}^{+}$.

Existing ATAPE approaches rely on switch-/stage-control routing on MINs by either S- or D-routing.

Correctness of the proposed ATAPE functions on d-nary-switch MINs⁺${}^{+}$ and a crossbar of MIN⁺${}^{+}$ are proven.

Experimental results are confirmed fruitfully for N=64$N=64$ to 16384 processors with the significant speedup.