Configurable memristive logic block for memristive-based FPGA architectures

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• 作者：Patrick W.C. Ho ; ^{kecx2pha@nottingham.edu.my} ; Haider Abbas F. Almurib ; T. Nandha Kumar
• 关键词：FPGA Architecture ; Memristor ; Logic block ; Switch block ; Configurable logic block
• 刊名：Integration, the VLSI Journal
• 出版年：2017
• 出版时间：January 2017
• 年：2017
• 卷：56
• 期：Complete
• 页码：61-69
• 全文大小：1042 K
• 卷排序：56

文摘

Configurable Memristive Logic Block (CMLB) that uses memristive circuits is proposed. CMLB is suitable for use in memristive-based FPGA architectures. Memristive D Flip-Flop, Memristive Switch Matrix, and Memristive Logic Slice. CMLB shows a reduction of 8.6% of device area and 1.094 times lesser critical path.