Pipelining data-dependent tasks in FPGA-based multicore architectures

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• 作者：Ali Azarian ; ^{azarian@fe.up.pt" class="auth_mail" title="E-mail the corresponding author} ; ^{azarian.ali@gmail.com" class="auth_mail" title="E-mail the corresponding author} ; ^{pro10002@fe.up.pt" class="auth_mail" title="E-mail the corresponding author}Author Vitae ; Joã ; o M.P. Cardoso ^{jmpc@acm.org" class="auth_mail" title="E-mail the corresponding author}Author Vitae
• 关键词：Multicore architectures ; Task-level pipelining ; FPGA ; Producer/consumer data communication
• 刊名：Microprocessors and Microsystems
• 出版年：2016
• 出版时间：May 2016
• 年：2016
• 卷：42
• 期：Complete
• 页码：165-179
• 全文大小：3052 K

文摘

In recent years, there has been increasing interest in using task-level pipelining to accelerate the overall execution of applications mainly consisting of producer/consumer tasks. This paper proposes fine- and coarse-grained data synchronization approaches to achieve pipelining execution of producer/consumer tasks in FPGA-based multicore architectures. Our approaches are able to speedup the overall execution of successive, data-dependent tasks, by using multiple cores and specific customization features provided by FPGAs. An important component of our approach is the use of customized inter-stage buffer schemes to communicate data and to synchronize the cores associated with the producer/consumer tasks. We propose techniques to reduce the number of accesses to external memory in our fine-grained data synchronization approach. The experimental results show the feasibility of the approach in both in-order and out-of-order producer/consumer tasks. Moreover, the results using our approach reveal noticeable performance improvements for a number of benchmarks over a single core implementation without using task-level pipelining.