Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K

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• 作者：Bruna Cardoso Paz^a ; ^{bcpaz@fei.edu.br} ; Mikaë ; l Cassé ; ^b ; Sylvain Barraud^b ; Gilles Reimbold^b ; Maud Vinet^b ; Olivier Faynot^b ; Marcelo Antonio Pavanello^a
• 关键词：Analog performance ; Nanowires ; Fin width influence ; Temperature influence ; Mobility
• 刊名：Solid-State Electronics
• 出版年：2017
• 出版时间：February 2017
• 年：2017
• 卷：128
• 期：Complete
• 页码：60-66
• 全文大小：1322 K
• 卷排序：128

文摘

This work presents an analysis of the performance of silicon triple gate SOI nanowires aiming the investigation of analog parameters for both long and short channel n-type and p-MOSFETs. Several nanowires with fin width as narrow as 9.5 nm up to quasi-planar MOSFETs 10 μm-wide are analyzed. The fin width influence on the analog parameters is studied for n-type and p-MOSFETs with channel lengths of 10 μm and 40 nm, at room temperature. The temperature influence is analyzed on the analog performance down to 100 K for long channel n-MOSFETs by comparing the quasi-planar device to the nanowire with fin width of 14.5 nm. The intrinsic voltage gain, transconductance and output conductance are the most important figures of merit in this work. An explicit correlation between these figures of merit and the mobility behavior with temperature is demonstrated.