文摘
A testable parity preserving full adder (t-Adder) is designed considering its primary outputs. Reliability issue is addressed with the success of 100% fault coverage with only 3 (three) test vectors. The power dissipation of the t-Adder is analysed which ensures low power consumption. To make robust fault secure t-Adder, path fault secure (PFS) scheme (first time in QCA circuit) is riveted to it. Further, t-Adder is used to design a simple testable ALU with high logical depth.