TCAD performance analysis of high-K dielectrics for gate all around InAs nanowire transistor considering scaling of gate dielectric thickness
详细信息 查看全文
- 作者：Richa Gupta 1richagupta@gmail.com" class="auth_mail" title="E-mail the corresponding author ; Rakesh Vaid ; rakeshvaid@ieee.org" class="auth_mail" title="E-mail the corresponding author
- 关键词：Gate All Around (GAA) ; Lanthanum oxide (La2O3) ; Drain Induced Barrier Lowering (DIBL) ; Effective oxide thickness (EOT) ; Nanowire FET (NWFET) ; Subthreshold slope (SS)
- 刊名：Microelectronic Engineering
- 出版年：2016
- 出版时间：1 July 2016
- 年：2016
- 卷：160
- 期：Complete
- 页码：22-26
- 全文大小：671 K
文摘
- •
Performance of GAA InAs nanowire transistor has been studied using SiO2, ZrO2, HfO2 and La2O3 as gate dielectrics.
- •
La2O3 shows improved device performance in terms of Ion, Ioff, gm and Ion/Ioff
- •
La2O3 has exceptional capability of suppressing the short channel effects (SCEs).
- •
Problem of leakage current associated with thinning of gate oxide has been solved by La2O3.
- •
La2O3 as gate dielectric could be used for ultra-fast, low power and high performance nanowire transistors.