Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology

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• 作者：David Alvarez ; Kiran Chatty ; Christian Russ ; Michel J. Abou-Khalil ; Junjun Li ; Robert Gauthier ; Kai Esmark ; Ralph Halbach ; Christopher Seguin
• 刊名：Microelectronics Reliability
• 出版年：2009
• 出版时间：December 2009
• 年：2009
• 卷：49
• 期：12
• 页码：1417-1423
• 全文大小：997 K

文摘

Decrease of the drain silicide-blocking-to-gate spacing in gate-silicided-ESD-NMOSFETs improves the TLP and HBM failure levels up to 30 % , while no effect is observed when decreasing the source silicide-blocking-to-gate spacing. Failure analysis and simulation results show that current crowding in the drain silicide region accounts for the difference in failure current for the devices.