Novel low-cost and fault-tolerant reversible logic adders
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- 作者：Mojtaba Valinataj ; m.valinataj@nit.ac.ir" class="auth_mail" title="E-mail the corresponding authorAuthor Vitae ; Mahboobeh MirshekarAuthor Vitae ; Hamid JazayeriAuthor Vitae
- 关键词：Reversible logic ; Parity preserving gates ; Fault-tolerance ; Low-power CMOS ; Binary coded decimal adder ; Carry skip adder ; Carry look-ahead adder
- 刊名：Computers & Electrical Engineering
- 出版年：2016
- 出版时间：July 2016
- 年：2016
- 卷：53
- 期：Complete
- 页码：56-72
- 全文大小：1995 K
文摘
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A new low-cost gate is proposed with the quantum cost of 10 to be used as a parity preserving full adder with the minimum hardware complexity so far.
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New fault-tolerant reversible CLA, CSK and BCD adders are proposed with better design criteria.
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CMOS transistor-based implementation of the proposed designs is investigated.
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A new more precise delay computation is presented as an important criterion to be utilized in the comparisons.