Two-step pulse-shrinking time-to-digital converter

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• 作者：Young Jun Park ; Fei Yuan ; ^{fyuan@ryerson.ca}
• 关键词：Time-to-digital converters (TDCs) ; Pulse-shrinking TDCs
• 刊名：Microelectronics Journal
• 出版年：2017
• 出版时间：February 2017
• 年：2017
• 卷：60
• 期：Complete
• 页码：45-54
• 全文大小：2183 K
• 卷排序：60

文摘

This paper presents a two-step pulse-shrinking time-to-digital converter (TDC) consisting of a 4-stage coarse pulse-shrinking TDC with per-stage shrinkage 1 ns and a 4-stage fine pulse-shrinking TDC with per-stage shrinkage 250 ps. A simple residual time extraction scheme is proposed to extract the residual pulse of the coarse TDC. The characteristics of the TDC including mismatch and noise-induced timing errors, timing errors of delay blocks, conversion time, power consumption, and silicon consumption are analyzed in detail. The proposed TDC was implemented in an IBM 130 nm 1.2 V CMOS technology. Simulation results show that the proposed TDC offers 1.4 ns conversion time, 1 LSB DNL and INL, and figure-of-merit (FoM) of 0.163 pJ/step. Some measurement results of the proposed TDC are also presented.