The characterization and application of a low resource FPGA-based time to digital converter
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- 作者：Aless ; ro Balla ; Matteo Mario Beretta ; Paolo Ciambrone ; Maurizio Gatta ; Francesco Gonnella ; Lorenzo Iafolla ; Matteo Mascolo ; Roberto Messi ; Dario Moricciani ; Domenico Riondino
- 关键词：DA桅NE ; DAQ ; FPGA ; HEP ; KLOE-2 ; TDC
- 刊名：Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
- 出版年：1 March, 2014
- 年：2014
- 卷：739
- 期：Complete
- 页码：75-82
- 全文大小：828 K
文摘
Time to Digital Converters (TDCs) are very common devices in particles physics experiments. A lot of 鈥渙ff-the-shelf鈥?TDCs can be employed but the necessity of a custom DAta acQuisition (DAQ) system makes the TDCs implemented on the Field-Programmable Gate Arrays (FPGAs) desirable. Most of the architectures developed so far are based on the tapped delay lines with precision down to 10 ps, obtained with high FPGA resources usage and non-linearity issues to be managed. Often such precision is not necessary; in this case TDC architectures with low resources occupancy are preferable allowing the implementation of data processing systems and of other utilities on the same device. In order to reconstruct 纬纬 physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a 32 channel TDC with a precision of 255 ps and low non-linearity effects along with an embedded data acquisition system and the interface to the online FARM of KLOE-2. The TDC is based on a low resources occupancy technique: the 4脳Oversampling technique which, in this work, is pushed to its best resolution and its performances were exhaustively measured.