Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model

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• 作者：Omnia S. Fadl^a ; ^{O_sayed83@yahoo.com" class="auth_mail" title="E-mail the corresponding author} ; Mohamed F. Abu-Elyazeed^a ; Mohamed B. Abdelhalim^b ; Hassanein H. Amer^c ; Ahmed H. Madian^d
• 关键词：CMOS combinational logic circuits ; Logic pictures ; Real-delay model ; Switching activity ; Dynamic power estimation ; Toggle rate
• 刊名：Journal of Advanced Research
• 出版年：2016
• 出版时间：January 2016
• 年：2016
• 卷：7
• 期：1
• 页码：89-94
• 全文大小：459 K

文摘

Dynamic power estimation is essential in designing VLSI circuits where many parameters are involved but the only circuit parameter that is related to the circuit operation is the nodes’ toggle rate. This paper discusses a deterministic and fast method to estimate the dynamic power consumption for CMOS combinational logic circuits using gate-level descriptions based on the Logic Pictures concept to obtain the circuit nodes’ toggle rate. The delay model for the logic gates is the real-delay model. To validate the results, the method is applied to several circuits and compared against exhaustive, as well as Monte Carlo, simulations. The proposed technique was shown to save up to 96% processing time compared to exhaustive simulation.