Switched-capacitor decimation filter design using time-multiplexing and polyphase decomposition of transfer functions with low denominator orders

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• 作者：A. Petraglia ; F.A.P. Barú ; qui ; J.S. Pereira
• 关键词：CMOS analog integrated circuits ; Multirate ; Polyphase decomposition ; Switched-capacitor filters
• 刊名：Microelectronics Journal
• 出版年：2009
• 出版时间：December 2009
• 年：2009
• 卷：40
• 期：12
• 页码：1673-1680
• 全文大小：1175 K

文摘

A new switched-capacitor decimation filter design technique is presented. Based on a combination of the polyphase decomposition of IIR low-pass transfer functions having small denominator order and time-multiplexed operational transconductance amplifiers, the filter presents very low sensitivity to transfer function coefficients. It suits analog front-end systems by providing signal conditioning and relaxing the filtering requirements in converting between continuous-time and discrete-time signals. A prototype decimation filter has been designed and fabricated in a standard CMOS process to verify the proposed approach. In fully differential design, the filter has a die area of 2.8 mm², dissipates 67.2 mW out of a 5 V power supply and achieves a dynamic range of 58 dB at 1 % THD. Experimental measurements are found in close agreement with theory.