A threshold voltage model of short-channel fully-depleted recessed-source/drain (Re-S/D) UTB SOI MOSFETs including substrate induced surface potential effects
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- 作者：Ajit Kumar ; Pramod Kumar Tiwari ; tiwarip@nitrkl.ac.in" class="auth_mail
- 关键词：Evanescent mode analysis ; SISP ; Silicon-on-insulator ; Recessed-source/drain (Re-S/D) ; DIBL
- 刊名：Solid-State Electronics
- 出版年：May 2014
- 年：2014
- 卷：95
- 期：Complete
- 页码：52-60
- 全文大小：1424 K
文摘
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A short channel threshold voltage model is presented for Re-S/D SOI MOSFETs.
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The effect of substrate induced surface potential is considered in modeling.
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The effect of substrate bias voltage is demonstrated on threshold voltage.
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At shorter channel length, back surface of silicon body gets inverted earlier.
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The front/back channel dominance is studied with device parameters.