Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits

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• 作者：S. Strangio^a ; ^{seb88str@gmail.com} ; P. Palestri^a ; M. Lanuzza^b ; D. Esseni^a ; F. Crupi^b ; L. Selmi^a
• 关键词：III-V ; TFET ; Full adders ; Ripple carry adders
• 刊名：Solid-State Electronics
• 出版年：2017
• 出版时间：February 2017
• 年：2017
• 卷：128
• 期：Complete
• 页码：37-42
• 全文大小：739 K
• 卷排序：128

文摘

In this work, a benchmark for low-power digital applications of a III-V TFET technology platform against a conventional CMOS FinFET technology node is proposed. The analysis focuses on full-adder circuits, which are commonly identified as representative of the digital logic environment. 28T and 24T topologies, implemented in complementary-logic and transmission-gate logic, respectively, are investigated. Transient simulations are performed with a purpose-built test-bench on each single-bit full adder solution. The extracted delays and energy characteristics are post-processed and translated into figures-of-merit for multi-bit ripple-carry-adders. Trends related to the different full-adder implementations (for the same device technology platform) and to the different technology platforms (for the same full-adder topology) are presented and discussed.