Processor-level reliability simulator for time-dependent gate dielectric breakdown

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• 作者：Chang-Chih ChenAuthor Vitae ; Taizhi LiuAuthor Vitae ; Soonyoung ChaAuthor Vitae ; Linda Milor ; ^{linda.milor@ece.gatech.edu" class="auth_mail" title="E-mail the corresponding author}Author Vitae
• 关键词：Microprocessor ; Modeling ; Timing analysis ; Cache ; Gate oxide breakdown ; Time-dependent dielectric breakdown
• 刊名：Microprocessors and Microsystems
• 出版年：2015
• 出版时间：November 2015
• 年：2015
• 卷：39
• 期：8
• 页码：950-960
• 全文大小：5124 K

文摘

Time-dependent gate dielectric breakdown (TDDB) is a leading reliability concern for modern microprocessors. In this paper, a framework is proposed to analyze the impact of TDDB on state-of-art microprocessors and to estimate microprocessor lifetimes due to TDDB. Our methodology finds the detailed electrical stress and temperature of each device within a microprocessor system running a variety of standard benchmarks. Combining the electrical stress profiles, thermal profiles, and device-level models, we perform timing analysis on the critical paths of a microprocessor using our methodology to characterize microprocessor performance degradation due to TDDB and to estimate the lifetime distribution of logic blocks. In addition, we study DC noise margins in conventional 6T SRAM cells as a function of TDDB degradation to estimate memory lifetime distributions. The lifetimes of memory blocks are then combined with the lifetimes of logic blocks to provide an estimate of the system lifetime distribution.