Ultra shallow P+/N junctions using plasma immersion ion implantation and laser annealing for sub 0.1 μm CMOS devices
详细信息    查看全文
文摘
Classical beam line ion implantation is limited to low energies and cannot achieve P+/N junctions requested for <45 nm ITRS node. RTA (rapid thermal annealing) needs to be improved for dopants activation and damage reductions. Spike annealing process also induces a large diffusion mainly due to TED (transient enhanced diffusion).

Compared to conventional beam line ion implantation limited to a minimum energy implantation of 200 eV, plasma immersion ion implantation (PIII) is an emerging technique to get ultimate shallow profiles (as-implanted) due to no lower limitation of energy and high dose rate. On the another hand, laser thermal processing (LTP) allows to obtain very shallow junction with no TED, abrupt profile and activated depth control.

In this paper, we show the implementation of the BF3 PIII associated with the LTP. Ions from plasma have been implanted in 200 mm n-type silicon wafers with energies from 100 eV to 1 keV and doses from 3E14 to 5E15 at/cm2 using PULSION® (IBS PIII prototype). Then, wafers have been annealed using SOPRA VEL 15 XeCl excimer lasers (l = 308 nm, 200 ns, 15 J/pulse) with energy density from 1 to 2.5 J/cm2 and 1, 3 or 10 shots. The samples have been characterized at CEA LETI by secondary ion mass spectrometry (SIMS) combined with four points probe sheet resistance measurements.

© 2004-2018 中国地质图书馆版权所有 京ICP备05064691号 京公网安备11010802017129号

地址:北京市海淀区学院路29号 邮编:100083

电话:办公室:(+86 10)66554848;文献借阅、咨询服务、科技查新:66554700