A PLL-based synthesizer for tunable digital clock generation in a continuous-time Σ
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- 作者：Jokin Segundo ; Luis Quintanilla ; Jesú ; s Arias ; Lourdes Enrí ; quez ; Jesú ; s M. Herná ; ndez ; José ; Vicente
- 关键词：Phase locked loop ; Clock generation ; Ring oscillator ; Phase noise ; Continuous-time ; none ; color ; black"" href=""/science?_ob=MathURL&_method=retrieve&_udi=B6V1M-4T1Y3KM-1&_mathId=mml57&_user=10&_cdi=5678&_pii=S016
- 刊名：Integration, the VLSI Journal
- 出版年：2009
- 出版时间：January 2009
- 年：2009
- 卷：42
- 期：1
- 页码：24-33
- 全文大小：1888 K
文摘
In this paper, the design and implementation of a tunable clock synthesizer for driving two continuous-time ΣΔ ADCs has been carried out. A PLL-based solution, whose phase noise requirements are obtained from system level simulations, was implemented in a CMOS technology. The frequency of the clock ranges from 12 to 256 MHz with a minimum tuning step of . The PLL phase noise is kept below at 1 MHz offset for the entire output range, while drawing 2.2–5.6 mA from a 3.3 V supply voltage.