Simulation of the electrostatic and transport properties of 3D-stacked GAA silicon nanowire FETs

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• 作者：F.G. Ruiz ; ^a ; ^{franruiz@ugr.es} ; I.M. Tienda-Luna^a ; A. Godoy^a ; C. Sampedro^a ; F. Gá ; miz^a ; L. Donetti^a
• 关键词：Multi-channel nanowires ; Multiple-gate devices ; Gate-all-Around (GAA) MOSFETs ; Silicon-on-Insulator ; Electron mobility
• 刊名：Solid-State Electronics
• 出版年：2011
• 出版时间：May 2011
• 年：2011
• 卷：59
• 期：1
• 页码：62-67
• 全文大小：669 K

文摘

In this work, both the electrostatic and transport features of 3D-stacked Gate-all-Around silicon nanowires are studied using simulations based on a self-consistent solution of the two-dimensional Poisson and Schrödinger equations. A comprehensive analysis of the effect of the strain induced by the fabrication process of such devices is carried out and a comparison made with a reference trigate device. It is shown that stacked nanowires can be a good alternative to trigate MOSFETs for sub-22 nm technology nodes, due to the increased gate electrostatic control of the channel of the Gate-all-Around architecture and to the higher total charge that can be achieved for the same wafer surface. It is also shown that the electron mobility calculated for unstrained stacked NWs is lower than that of trigate devices, but the strain induced in the channels by the SiGe layers during the fabrication process of stacked NWs can overturn this situation.