Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries

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• 作者：Donald Shaw ; Dhamin Al-Khalili and Come Rozon
• 关键词：Fault models ; VHDL ; Defect to fault mapping ; Model generation tool
• 刊名：Integration, the VLSI Journal
• 出版年：2006
• 出版时间：July 2006
• 年：2006
• 卷：39
• 期：4
• 页码：382-406
• 全文大小：401 K

文摘

Popular generic fault models, which exhibit limited realism for different IC technologies, have been widely misused due to their simplicity and cost-effective implementation. This paper introduces a system for deriving accurate, technology specific fault models that are based on analog defect simulation. This technique, though used in other research efforts, is formally defined in this paper and a systematic approach is developed. It is supported by a new software tool that provides a push-button solution for the previously tedious task of obtaining accurate ASIC cell defect to fault mappings. Furthermore, upon completion of the cell defect analysis, the tool automatically generates VITAL compliant, defect-injectable, VHDL cell models.