On the need for a new ESD verification methodology to improve the reliability of ICs in advanced 28nm UTBB FD-SOI technology
详细信息 查看全文
- 作者：B. Vialea ; b ; benjamin.viale@st.com" class="auth_mail" title="E-mail the corresponding author ; M. Fera ; L. Couraua ; P. Galya ; B. Allardb
- 关键词：ESD network ; Verification tool ; ESD protection strategy ; Custom I/O ring ; IC reliability ; 28nm UTBB FD-SOI
- 刊名：Microelectronics Reliability
- 出版年：2016
- 出版时间：September 2016
- 年：2016
- 卷：64
- 期：Complete
- 页码：101-108
- 全文大小：2821 K
文摘
- •
A method to identify and verify on-chip ESD protection networks is described.
- •
The robustness of the method is tested on two cases involving different ESD protection strategies.
- •
The ESD network overview is given in the form of a directed graph.
- •
ESD path existence results are summarized in the form of a test-plan matrix.