Investigating degradation behavior of hole-trapping effect under static and dynamic gate-bias stress in a dual gate a-InGaZnO thin film transistor with etch stop layer
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- 作者：Po-Yung Liaoa ; Ting-Chang Changa ; b ; tcchang3708@gmail.com" class="auth_mail" title="E-mail the corresponding author ; Tien-Yu Hsieha ; Ming-Yen Tsaic ; Bo-Wei Chenc ; Ann-Kuo Chuc ; Cheng-Hsu Choud ; Jung-Fang Changd
- 关键词：Indium&ndash ; gallium&ndash ; zinc oxide ; Dual gate thin film transistors ; Etch stop layer ; Negative gate bias illumination stress
- 刊名：Thin Solid Films
- 出版年：2016
- 出版时间：31 March 2016
- 年：2016
- 卷：603
- 期：Complete
- 页码：359-362
- 全文大小：830 K
文摘
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Static and dynamic gate bias stresses are imposed on dual gate InGaZnO TFTs.
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Top-gate NBIS operation exhibits on-state current increases without VT shift.
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The degradation behavior of top-gate NBIS is due to hole-trapping in the ESL.
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The degradation is dependent on the frequency of the top gate pulses.
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The VT shift increases with decreasing frequency of the top gate pulses.