Threshold voltage variation-immune FinFET design with metal-interlayer-semiconductor source/drain structure
详细信息 查看全文
- 作者：Changho Shina ; Jeong-Kyu Kima ; Changhwan Shinb ; Jong-Kook Kima ; Hyun-Yong Yua ; yuhykr@korea.ac.kr" class="auth_mail" title="E-mail the corresponding author
- 关键词：CMOS ; FinFET ; Metal-interlayer-semiconductor ; Random dopant fluctuation ; Variation
- 刊名：Current Applied Physics
- 出版年：2016
- 出版时间：June 2016
- 年：2016
- 卷：16
- 期：6
- 页码：618-622
- 全文大小：1758 K
文摘
- •
The impact of RDF on 10-nm Si FinFET with M-I-S S/D structure is investigated using 3-D TCAD simulation.
- •
To explore a desirable aspect ratio of the fin for Vth variation-immune FinFET, device performances are evaluated.
- •
To suppress Vth variation even more, a n+-ZnO interlayer can be introduced onto the S/D region of the FinFET.