FPGA Implementation of Spatial Image Filters using Xilinx System Generator
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- 作者：V. Elamaran ; elamaran@ece.sastra.edu ; Angam Praveen angam.praveen@gmail.com ; Medapati Srinivasa Reddy ; Lanka Venkata Aditya ; Kunta Suman
- 关键词：Spatial Filtering ; FPGA ; System Generator ; Co-simulation ; 2D Convolution
- 刊名：Procedia Engineering
- 出版年：2012
- 出版时间：2012
- 年：2012
- 卷：38
- 期：Complete
- 页码：2244-2249
- 全文大小：2261 K
文摘
The objective of this paper is to design, model, simulate and synthesis of Spatial Filtering Techniques, in which the operation is performed within neighborhood of a pixel. Recent increases in Filed Programmable Gate Array (FPGA) performance and size offer a new hardware acceleration opportunity. The convolution filtering operations are implemented using Xilinx System Generator (XSG) which is the industry's leading high-level tool for designing high-performance DSP systems using FPGAs. The designs are modeled using XSG Block set and synthesized onto Virtex 6 xc6vs315t-3ff156 FPGA device. The algorithms are validated using hardware co-simulation method.