Configurable interleaving network supports any 2i-input (0≤i≤n) network. A new low complexity address generator for interleaving.
Optimized decoding schedule reduces performance loss caused by parallel turbo decoding.
Configurable memory architecture is proposed to avoid memory access contention. Dual-mode ACS unit for both radix-2 and radix-4 processing.
The proposed parallel turbo decoder supports all 188 block sizes in LTE.