Low area 4-bit 5 MS/s flash-type digitizer for hybrid-pixel detectors - Design study in 180 nm and 40 nm CMOS

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• 作者：Piotr Otfinowski ; ^{potfin@agh.edu.pl" class="auth_mail" title="E-mail the corresponding author} ; Pawel Grybos
• 关键词：Flash ADC ; Dynamic offset correction ; Low-area ; Pixel ADC
• 刊名：Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
• 出版年：2015
• 出版时间：11 November 2015
• 年：2015
• 卷：800
• 期：Complete
• 页码：104-110
• 全文大小：2044 K

文摘

We report on the design of a 4-bit flash ADC with dynamic offset correction dedicated to measurement systems based on a pixel architecture. The presented converter was manufactured in two CMOS technologies: widespread and economical 180 nm and modern 40 nm process. The designs are optimized for the lowest area occupancy resulting in chip areas of 160×55 µm² and 35×25 µm². The experimental results indicate integral nonlinearity of +0.35/−0.21 LSB and +0.28/−0.25 LSB and power consumption of 52 µW and 17 µW at 5 MS/s for the prototypes in 180 nm and 40 nm technologies respectively.