Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits

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• 作者：Ioannis Savidis ; Syed M. Alam ; Ankur Jain ; Scott Pozder ; Robert E. Jones ; Ritwik Chatterjee
• 关键词：3D integration ; Vias ; TSV ; Electrical characterization ; Via parasitics ; IO delay
• 刊名：Microelectronics Journal
• 出版年：2010
• 出版时间：January 2010
• 年：2010
• 卷：41
• 期：1
• 页码：9-16
• 全文大小：540 K

文摘

The integration of chips in the third dimension has been explored to address various physical and system level limitations currently undermining chip performance. In this paper, we present a comprehensive analysis of the electrical properties of through silicon vias and microconnects with an emphasis on single via characteristics as well as inter-TSV capacitive and inductive coupling in the presence of either a neighboring ground tap or a grounded substrate back plane. We also analyze the impact of technology scaling on TSV electrical parasitics, and investigate the power and delay trend in 3-D interstratum IO drivers with those of global wire in 2-D circuits over various technology nodes. We estimate the global wire length necessary to produce an equivalent 3-D IO delay, a metric useful in early stage design tools for 3D floorplanning that considers the electrical characteristics of 3D connections with TSVs and microconnects.