Charge-based compact analytical model for triple-gate junctionless nanowire transistors
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- 作者：F. Á ; vila-Herreraa ; favila@cinvestav.mx" class="auth_mail" title="E-mail the corresponding author ; B.C. Pazb ; A. Cerdeiraa ; M. Estradaa ; M.A. Pavanellob
- 关键词：3-D compact model ; Triple-gate JLT ; Nanowire JLT ; SCE ; Fin height capacitance ; Threshold voltage
- 刊名：Solid State Electronics
- 出版年：2016
- 出版时间：August 2016
- 年：2016
- 卷：122
- 期：Complete
- 页码：23-31
- 全文大小：1520 K
文摘
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A compact analytical model for triple gate junctionless transistors is developed.
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Junctionless devices from double gate down to nanowires transistors are modeled.
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An analytical expression for threshold voltage is presented.
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Short channel effects, mobility degradation and series resistance are covered.
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The model validation is performed with simulated and experimental results.