Performance optimization of nanoscale junctionless transistors through varying device design parameters for ultra-low power logic applications
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- 作者：Debapriya Roy ; Abhijit Biswas ; abiswas5@rediffmail.com" class="auth_mail" title="E-mail the corresponding author
- 关键词：Delay ; Junctionless transistors ; Logic performance ; Low-power ; ON-current ; Subthreshold slope
- 刊名：Superlattices and Microstructures
- 出版年：2016
- 出版时间：September 2016
- 年：2016
- 卷：97
- 期：Complete
- 页码：140-154
- 全文大小：2202 K
文摘
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Low power performance of nanoscale junctionless (JL) MOSFETs is optimized.
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Impact of channel doping, underlap spacer, etc. on performance metrics is studied.
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ON-current for a fixed OFF-current, subthreshold swing & delay are optimized.
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Our proposed JL MOSFETs outperform Si FinFETs at channel length of 34 nm.