Transistor optimisation for a low cost, high performance 0.13 μm CMOS technology
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- 作者：Augendre ; E. ; Kubicek ; S. ; De Keersgieter ; A. ; Mertens ; S. ; Lindsay ; R. ; Verbeeck ; R. ; Van Laer ; J. ; et. al.
- 关键词：CMOS processing ; Nitrided oxide ; Boron ion implantation ; BF2 ion implantation ; Spike rapid thermal anneal
- 刊名：Solid-State Electronics
- 出版年：2002
- 出版时间：July, 2002
- 年：2002
- 卷：46
- 期：7
- 页码：959-963
- 全文大小：488 K
文摘
This paper discusses the optimisation of a high performance, low cost 0.13 μm CMOS technology with a view on its further scaling to the 100 nm technology node. The focus is mainly on gate oxide (thickness and nitridation method), deep junction implants and annealing. It is shown that in order to take the full benefit of gate oxide thinning, low energy boron implants and spike rapid thermal anneal are mandatory for pMOS devices. The same route gives also promising results for nMOS transistors when gate predoping is used to reduce gate depletion.