Two-level main memory co-design: Multi-threaded algorithmic primitives, analysis, and simulation

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• 作者：Michael A. Bender^a ; ^{bender@cs.stonybrook.edu}Author Vitae ; Jonathan W. Berry^b ; ^{jberry@sandia.gov}Author Vitae ; Simon D. Hammond^b ; ^{sdhammo@sandia.gov}Author Vitae ; K. Scott Hemmert^b ; ^{kshemme@sandia.gov}Author Vitae ; Samuel McCauley^a ; ^{smccauley@cs.stonybrook.edu}Author Vitae ; Branden Moore^b ; ^{bjmoor@sandia.gov}Author Vitae ; Benjamin Moseley^c ; ^{moseleyb85@gmail.com}Author Vitae ; Cynthia A. Phillips^b ; ^{caphill@sandia.gov}Author Vitae ; David Resnick^b ; ^{drresni@sandia.gov}Author Vitae ; Arun Rodrigues^b ; ^{afrodni@sandia.gov}Author Vitae
• 关键词：Two-level memory ; High-bandwidth memory ; Sorting ; kk-means clustering
• 刊名：Journal of Parallel and Distributed Computing
• 出版年：2017
• 出版时间：April 2017
• 年：2017
• 卷：102
• 期：Complete
• 页码：213-228
• 全文大小：2040 K
• 卷排序：102

文摘

Emerging architectures feature high-bandwidth scratchpad memory that is not cache. We adapt a classical external-memory model to this context. We design and analyze algorithms for sorting and k-means using this model. We validate our predictions with simulation and/or a custom machine.