Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker

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• 作者：G. Rizzo^p ; ^r ; ^{rizzo@pi.infn.it} ; D. Comott^a ; M. Manghisoni^a ; ^b ; V. Re^a ; ^b ; G. Traversi^a ; ^b ; L. Fabbri^c ; ^d ; A. Gabrielli^c ; ^d ; F. Giorgi^d ; G. Pellegrini^d ; C. Sbarra^d ; N. Semprini-Cesari^c ; ^d ; S. Valentinetti^c ; ^d ; M. Villa^c ; ^d ; A. Zoccoli^c ; ^d ; A. Berra^e ; ^f ; D. Lietti^e ; ^f ; M. Prest^e ; ^f ; A. Bevan^g ; F. Wilson^h ; G. Beck^g ; J. Morris^g ; F. Gannaway^g ; R. Cenciⁱ ; L. Bombelli^k ; ^l ; M. Citterio^l ; S. Coelli^l ; C. Fiorini^k ; ^l ; V. Liberali^j ; ^l ; M. Monti^l ; B. Nasri^k ; ^l ; N. Neri^l ; F. Palombo^j ; ^l ; A. Stabile^j ; ^l ; G. Balestri^r ; G. Batignani^p ; ^r ; A. Bernardelli^r ; S. Bettarini^p ; ^r ; F. Bosi^r ; G. Casarosa^p ; ^r ; M. Ceccanti^r ; F. Forti^p ; ^r ; M.A. Giorgi^p ; ^r ; A. Lusiani^q ; ^r ; P. Mammini^r ; F. Morsani^r ; B. Oberhof^p ; ^r ; E. Paoloni^p ; ^r ; A. Perez^r ; G. Petragnani^r ; A. Profeti^r ; A. Soldani^r ; J. Walsh^r ; M. Chrzaszcz^r ; ^y ; L. Gaioni^b ; A. Manazza^o ; ^b ; E. Quartieri^o ; ^b ; L. Ratti^o ; ^b ; S. Zucca^o ; ^b ; G. Alampi^t ; G. Cotto^s ; ^t ; D. Gamba^s ; ^t ; S. Zambito^s ; ^t ; G.-F. Dalla Betta^u ; ⁿ ; G. Fontana^u ; ⁿ ; L. Pancheri^u ; ⁿ ; M. Povoli^u ; ⁿ ; G. Verzellesiⁿ ; ^m ; M. Bomben^z ; L. Bosisio^v ; ^w ; P. Cristaudo^w ; L. Lanceri^v ; ^w ; B. Liberti^w ; I. Rashevskaya^w ; C. Stella^x ; ^w ; L. Vitale^v ; ^w
• 关键词：Solid state detectors ; Vertex detectors ; CMOS MAPS pixel sensors ; Hybrid pixels ; Charged particle tracking
• 刊名：Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
• 出版年：2013
• 出版时间：1 August, 2013
• 年：2013
• 卷：718
• 期：Complete
• 页码：283-287
• 全文大小：566 K

文摘

In the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius (about 1.5 cm), resolution of in both coordinates, low material budget , and the ability to withstand a background hit rate of several tens of . Thanks to an intense R&D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130 nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time stamping. Further MAPS performance improvements are currently under investigation with two different approaches: the INMAPS CMOS process, featuring a quadruple well and a high resistivity substrate, and 3D CMOS MAPS, realized with vertical integration technology. In both cases specific features of the processes chosen can improve charge collection efficiency, with respect to a standard DNW MAPS design, and allow to implement a more complex in-pixel logic in order to develop a faster readout architecture. Prototypes of MAPS matrix, suitable for application in the SuperB Layer0, have been realized with the INMAPS 180 nm process and the 130 nm Chartered/Tezzaron 3D process and results of their characterization will be presented in this paper.