A low-power fast tag comparator by modifying charging scheme of wide fan-in dynamic OR gates
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- 作者：Mahshid Nasseriana ; nasserian.mahshid@stu.um.ac.ir" class="auth_mail" title="E-mail the corresponding authorAuthor Vitae ; Mohammad Kafi-Kangia ; kafikangi.m@gmail.com" class="auth_mail" title="E-mail the corresponding authorAuthor Vitae ; Mohammad Maymandi-Nejada ; maymandi@um.ac.ir" class="auth_mail" title="E-mail the corresponding authorAuthor Vitae ; Farshad Moradib ; moradi@eng.au.dk" class="auth_mail" title="E-mail the corresponding authorAuthor Vitae
- 关键词：Dynamic logic ; Power-delay product ; Reduced power ; Wide fan-in
- 刊名：Integration, the VLSI Journal
- 出版年：2016
- 出版时间：January 2016
- 年：2016
- 卷：52
- 期：Complete
- 页码：129-141
- 全文大小：1858 K
文摘
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A new technique called MCSD is presented for reducing the power consumption of wide fan-in dynamic OR circuits.
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It has shown that in modern technology nodes using the MCSD technique, the power consumption of the OR gates can be effectively reduced without sacrificing other circuit parameters.
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An important benefit of the proposed approach is 98.7X reduction in power consumption of the gate load by limiting its switching activity.
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Using the proposed technique, a 40-bit Tag Compotator is designed that its power-delay product is reduced approximately by 49.4%.